公开(公告)号：US11335847B2

公开(公告)日：2022-05-17

申请号：US16072587

申请日：2017-01-17

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Eric Butaud ,  Eric Desbonnets

IPC: H01L41/312 ,  H01L41/08 ,  H03H9/02 ,  H03H9/00 ,  H03H3/02

Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

公开(公告)号：US20240397825A1

公开(公告)日：2024-11-28

申请号：US18790903

申请日：2024-07-31

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Eric Butaud ,  Eric Desbonnets

IPC: H10N30/072 ,  H03H3/02 ,  H03H9/00 ,  H03H9/02

Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

公开(公告)号：US20220247374A1

公开(公告)日：2022-08-04

申请号：US17597581

申请日：2020-03-26

Applicant: Soitec

Inventor： Isabelle Bertrand ,  Alexis Drouin ,  Isabelle Huyet ,  Eric Butaud ,  Morgane Logiou

IPC: H03H3/08 ,  H03H9/02

Abstract: A method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge trapping layer, the method comprising the following steps: —preparing the support comprising forming the trapping layer on a base substrate, the trapping layer having a hydrogen concentration of less than 10{circumflex over ( )}18 at/cm{circumflex over ( )}; —joining the support to a donor substrate by way of a dielectric layer having a hydrogen concentration of less than 10{circumflex over ( )}20 at/cm{circumflex over ( )}3 or comprising a barrier preventing the diffusion of hydrogen toward the trapping layer or having low hydrogen diffusivity; —removing part of the donor substrate to form the thin layer; the manufacturing method exposing the structure to a temperature below a maximum temperature of 1000° C. The present disclosure also relates to a structure obtained at the end of this method.

公开(公告)号：US20140346639A1

公开(公告)日：2014-11-27

申请号：US14372659

申请日：2013-01-14

Applicant: Soitec

Inventor： Francois Boedt ,  Roland Brun ,  Olivier Ledoux ,  Eric Butaud

IPC: H01L21/762 ,  H01L29/36 ,  H01L21/66

CPC classification number: H01L21/76254 ,  H01L22/12 ,  H01L22/20 ,  H01L29/36

Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.

Abstract translation: 本发明涉及一种用于制造半导体衬底的方法，其特征在于，其包括提供包括至少一个有用硅层的至少一个施主半导体衬底; 通过检查机检查供体基板，以便检测有用层是否包含尺寸大于或等于临界尺寸的新出现的空腔，所述临界尺寸严格小于44nm; 以及制造包括供体衬底的有用层的至少一部分的半导体衬底，如果考虑尺寸大于或等于临界尺寸的空腔，则供体衬底的有用层中的空腔的密度或数量低于 或等于临界缺陷密度或数量。

公开(公告)号：US20240030883A1

公开(公告)日：2024-01-25

申请号：US17907247

申请日：2021-03-24

Applicant: Soitec

Inventor： Arnaud Castex ,  Laurence Doutre-Roussel ,  Eric Butaud ,  Brice Tavel

IPC: H03H3/08 ,  H10N30/073 ,  H10N30/082 ,  H10N30/086

CPC classification number: H03H3/08 ,  H10N30/073 ,  H10N30/082 ,  H10N30/086

Abstract: A method of manufacturing a piezoelectric structure comprises providing a substrate of piezoelectric material, providing a carrier substrate, depositing a dielectric bonding layer at a temperature lower than or equal to 300° C. on a single side of the substrate of piezoelectric material, a step of joining the substrate of piezoelectric material to the carrier substrate via the dielectric bonding layer, a thinning step for forming the piezoelectric structure, which comprises a layer of piezoelectric material joined to a carrier substrate.

公开(公告)号：US20220158080A1

公开(公告)日：2022-05-19

申请号：US17649470

申请日：2022-01-31

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Eric Butaud ,  Eric Desbonnets

IPC: H01L41/312 ,  H01L41/08 ,  H03H9/02 ,  H03H9/00 ,  H03H3/02

Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

公开(公告)号：US12108678B2

公开(公告)日：2024-10-01

申请号：US17649470

申请日：2022-01-31

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Eric Butaud ,  Eric Desbonnets

IPC: H01L41/08 ,  H03H3/02 ,  H03H9/00 ,  H03H9/02 ,  H10N30/00 ,  H10N30/072

CPC classification number: H10N30/072 ,  H03H3/02 ,  H03H9/0009 ,  H03H9/02047 ,  H03H9/02574 ,  H10N30/708

Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

公开(公告)号：US09911641B2

公开(公告)日：2018-03-06

申请号：US14372659

申请日：2013-01-14

Applicant: Soitec

Inventor： Francois Boedt ,  Roland Brun ,  Olivier Ledoux ,  Eric Butaud

IPC: H01L21/762 ,  H01L21/66 ,  H01L29/36

CPC classification number: H01L21/76254 ,  H01L22/12 ,  H01L22/20 ,  H01L29/36

Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.