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    SOI device with source/drain extensions and adjacent shallow pockets
    2.
    发明授权
    SOI device with source/drain extensions and adjacent shallow pockets 有权
    具有源极/漏极延伸部分和相邻浅凹部的SOI器件

    公开(公告)号：US06541821B1

    公开(公告)日：2003-04-01

    申请号：US09732952

    申请日：2000-12-07

    申请人： Srinath Krishnan ,  Witold P. Maszara ,  Zoran Krivokapic

    发明人： Srinath Krishnan ,  Witold P. Maszara ,  Zoran Krivokapic

    IPC分类号： H01L2972

    CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

    摘要： A Silicon-on-Insulator (SOI) transistor includes an intrinsic body layer that is fully depleted when in a conductive state. The transistor includes a shallow pocket of dopants adjacent to each of its source and drain regions. The shallow pockets are of a conductivity type opposite to that of the source and drain regions and raise the threshold voltage of the transistor. The transistor also includes a deep pocket of dopants adjacent each of the source and drain regions to suppress the punch-through current.

    摘要翻译： 绝缘体上硅绝缘体（SOI）晶体管包括在导电状态下完全耗尽的本征体层。 晶体管包括与其源极和漏极区域中的每一个相邻的掺杂物的浅阱。 浅槽口具有与源极和漏极区域相反的导电类型，并提高晶体管的阈值电压。 晶体管还包括与源极和漏极区域中的每一个相邻的掺杂剂的深口袋，以抑制穿通电流。

    Ultra-thin fully depleted SOI device and method of fabrication
    5.
    发明授权
    Ultra-thin fully depleted SOI device and method of fabrication 有权
    超薄全耗尽SOI器件及其制造方法

    公开(公告)号：US06815297B1

    公开(公告)日：2004-11-09

    申请号：US10081361

    申请日：2002-02-21

    申请人： Zoran Krivokapic ,  Witold P. Maszara

    发明人： Zoran Krivokapic ,  Witold P. Maszara

    IPC分类号： H01L21336

    CPC分类号： H01L29/78696 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78618

    摘要： A fully depleted SOI FET and methods of formation are disclosed. The FET includes a layer of semiconductor material disposed over an insulating layer, the insulating layer disposed over a semiconductor substrate. A source, a drain and a body disposed between the source and the drain are formed from the layer of semiconductor material. The layer of semiconductor material is etched such that a thickness of the body is less than a thickness of the source and the drain and such that a recess is formed in the layer of semiconductor material over the body. A gate is formed at least in part in the recess. The gate defines a channel in the body and includes a gate electrode spaced apart from the body by a high-K gate dielectric.

    摘要翻译： 公开了一种完全耗尽的SOI FET及其形成方法。 FET包括设置在绝缘层上的半导体材料层，绝缘层设置在半导体衬底上。 设置在源极和漏极之间的源极，漏极和主体由半导体材料层形成。 蚀刻半导体材料层，使得主体的厚度小于源极和漏极的厚度，并且使得在半导体材料层上形成凹部。 门至少部分地形成在凹部中。 栅极限定了主体中的通道，并且包括通过高K栅极电介质与主体间隔开的栅电极。

    Formation of low thermal budget shallow abrupt junctions for semiconductor devices
    8.
    发明授权
    Formation of low thermal budget shallow abrupt junctions for semiconductor devices 有权
    形成半导体器件低热预算浅突点

    公开(公告)号：US06362063B1

    公开(公告)日：2002-03-26

    申请号：US09226773

    申请日：1999-01-06

    申请人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

    发明人： Witold P. Maszara ,  Srinath Krishnan ,  Shekhar Pramanick

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  H01L21/26506 ,  H01L21/26513

    摘要： A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the surface of the substrate by implanting an electrically inactive ion, such as germanium or silicon, into the substrate. The amorphous/crystalline interface between the amorphous layer and the base crystal substrate is located at the depth of the desired junction. A dopant species, such as boron, phosphorus or arsenic is implanted into the substrate so that peak concentration of the dopant is at least partially within the amorphous layer. The amorphous layer can be formed either before or after the implanting of the dopant species. A low temperature anneal is used to recrystallize the amorphous layer through solid phase epitaxy, which also activates the dopant within the amorphous layer. The dopant located beneath the original amorphous/crystalline interface remains inactive. Thus, an abrupt junction is formed at the depth of the original amorphous/crystalline interface. Formation of such a shallow abrupt junction is useful in devices such as diodes and transistors, including bipolar, MOSFET and CMOS, and may be used to form source drain extensions and halo regions. Subsequent processing of the substrate has a thermal budget that is approximately equal to or less than the temperature used for the low temperature anneal.

    摘要翻译： 在单晶衬底中形成浅的突点，例如在二极管中形成pn结或在晶体管中形成源极漏极延伸。 通过将非活性离子（例如锗或硅）注入到衬底中，在衬底的表面上形成非晶层。 非晶层和基底晶体之间的非晶/晶界面位于所需结的深度处。 掺杂物质如硼，磷或砷被注入到衬底中，使得掺杂剂的峰值浓度至少部分地在非晶层内。 可以在注入掺杂剂物质之前或之后形成非晶层。 低温退火用于通过固相外延重结晶非晶层，这也激活非晶层内的掺杂剂。 位于原始非晶/晶界面之下的掺杂剂保持不活动。 因此，在原始非晶/晶界面的深度处形成突变结。 形成这样一个浅的突变结可用在诸如二极管和晶体管的器件中，包括双极型，MOSFET和CMOS，并且可用于形成源极漏极延伸部分和卤素区域。 衬底的后续处理具有大约等于或小于用于低温退火的温度的热预算。

    Fast MOSFET with low-doped source/drain
    9.
    发明授权
    Fast MOSFET with low-doped source/drain 有权
    具有低掺杂源极/漏极的快速MOSFET

    公开(公告)号：US06238960B1

    公开(公告)日：2001-05-29

    申请号：US09483400

    申请日：2000-01-14

    申请人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

    发明人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

    IPC分类号： H01L21336

    CPC分类号： H01L29/66772 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

    摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.

    摘要翻译： 形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124） 氧化物（122）。 随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一 区域（60）和在其间具有沟道区（58）的第二区域（68）。 方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域 （60）和第二区域（68）中的源极区域（70）。 源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。 源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

    Fast Mosfet with low-doped source/drain
    10.
    发明授权
    Fast Mosfet with low-doped source/drain 有权
    具有低掺杂源/漏极的快速Mosfet

    公开(公告)号：US06060364A

    公开(公告)日：2000-05-09

    申请号：US260880

    申请日：1999-03-02

    申请人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

    发明人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

    摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.

    摘要翻译： 形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124） 氧化物（122）。 随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一 区域（60）和在其间具有沟道区（58）的第二区域（68）。 方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域 （60）和第二区域（68）中的源极区域（70）。 源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。 源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。