公开(公告)号：US20150162344A1

公开(公告)日：2015-06-11

申请号：US14621568

申请日：2015-02-13

申请人： Sunghae LEE ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

发明人： Sunghae LEE ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/311 ,  H01L21/283

CPC分类号： H01L27/11582 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7827

摘要： Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

摘要翻译： 提供三维半导体存储器件及其制造方法。 根据该方法，将牺牲层和绝缘层交替重复堆叠在基板上，并且形成贯穿牺牲层的最上层牺牲层的切割区域。 切割区域填充有非牺牲层。 将绝缘层和牺牲层图案化以形成模具图案。 模具图案包括切割区域中的绝缘图案，牺牲图案和非牺牲层。 牺牲图案可以用电极代替。 还提供了相关的半导体存储器件。

公开(公告)号：US20120248525A1

公开(公告)日：2012-10-04

申请号：US13401013

申请日：2012-02-21

申请人： Sunghae LEE ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

发明人： Sunghae LEE ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L27/11582 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7827

摘要： Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

摘要翻译： 提供三维半导体存储器件及其制造方法。 根据该方法，将牺牲层和绝缘层交替重复堆叠在基板上，并且形成贯穿牺牲层的最上层牺牲层的切割区域。 切割区域填充有非牺牲层。 将绝缘层和牺牲层图案化以形成模具图案。 模具图案包括切割区域中的绝缘图案，牺牲图案和非牺牲层。 牺牲图案可以用电极代替。 还提供了相关的半导体存储器件。

公开(公告)号：US20170287929A1

公开(公告)日：2017-10-05

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil KIM ,  Phil Ouk NAM ,  Gukhyon YON ,  Sunghae LEE ,  Woojin JANG ,  Dongchul YOO ,  Hunhyeong LIM ,  Junggeun JEE ,  Kihyun HWANG

发明人： Sunggil KIM ,  Phil Ouk NAM ,  Gukhyon YON ,  Sunghae LEE ,  Woojin JANG ,  Dongchul YOO ,  Hunhyeong LIM ,  Junggeun JEE ,  Kihyun HWANG

IPC分类号： H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

CPC分类号： H01L27/11582 ,  H01L21/0206 ,  H01L21/31116 ,  H01L27/115 ,  H01L27/1157 ,  H01L28/00 ,  H01L29/1037 ,  H01L29/40117

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.