公开(公告)号：US20090008725A1

公开(公告)日：2009-01-08

申请号：US11773160

申请日：2007-07-03

申请人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.

公开(公告)号：US20090294876A1

公开(公告)日：2009-12-03

申请号：US12541241

申请日：2009-08-14

申请人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

IPC分类号： H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.

摘要翻译： 提供了一种在高k栅极电介质/界面层的堆叠顶上形成正电的含金属覆盖层的方法，其避免化学和物理改变高k栅极电介质和界面层。 该方法包括在约400℃或更低的温度下化学气相沉积含正电性金属的前体。 本发明还提供半导体结构，例如MOSCAP和MOSFET，其包括在高k栅极电介质和界面层的堆叠顶上的化学气相沉积的正电性含金属覆盖层。 CVD正电金属覆盖层的存在不会物理或化学地改变高k栅极电介质和界面层。

公开(公告)号：US07863083B2

公开(公告)日：2011-01-04

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L21/266 ,  H01L21/425

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US20080311745A1

公开(公告)日：2008-12-18

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/44

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US20080166586A1

公开(公告)日：2008-07-10

申请号：US11621389

申请日：2007-01-09

申请人： Supratik Guha ,  Fenton R. McFeely ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  John J. Yurkas

IPC分类号： H01L29/12 ,  C23C16/00

CPC分类号： C23C16/04 ,  C23C16/30 ,  Y10T428/12528

摘要： A chemical vapor deposition (CVD) method for selectively depositing GeSb materials onto a surface of a substrate is provided in which a metal that is capable of forming an eutectic alloy with germanium is used to catalyze the growth of the GeSb materials. A structure is also provided that includes a GeSb material located on preselected regions of a substrate. In accordance with the present invention, the GeSb material is sandwiched between a lower metal layer used to catalyze the growth of the GeSb and an upper surface metal layer that forms during the growth of the GeSb material.

摘要翻译： 提供了一种用于选择性地将GeSb材料沉积到衬底表面上的化学气相沉积（CVD）方法，其中能够与锗形成共晶合金的金属用于催化GeSb材料的生长。 还提供了一种结构，其包括位于基底的预选区域上的GeSb材料。 根据本发明，GeSb材料夹在用于催化GeSb生长的下金属层和GeSb材料生长期间形成的上表面金属层之间。

公开(公告)号：US07439180B2

公开(公告)日：2008-10-21

申请号：US11495335

申请日：2006-07-28

申请人： Supratik Guha ,  Fenton R. McFeely ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  John J. Yurkas

IPC分类号： H01L21/44

CPC分类号： H01L21/28194 ,  C23C16/45563 ,  C23C16/4558 ,  H01L29/513 ,  H01L29/517

摘要： A dispenser system for use in atomic beam assisted metal organic chemical vapor deposition is provided as well as a method of depositing an ultra-thin film using the same. The inventive dispenser system includes an atomic source having an unimpeded line of site to a substrate and an annular metal organic chemical vapor deposition showerhead having a plurality of nozzles for delivering a precursor to the substrate. In accordance with the present invention, each of the nozzles present on the showerhead is angled to provide precursor beam trajectories that crossover and are non-intercepting.

公开(公告)号：US20080026575A1

公开(公告)日：2008-01-31

申请号：US11495335

申请日：2006-07-28

申请人： Supratik Guha ,  Fenton R. McFeely ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  John J. Yurkas

IPC分类号： H01L21/44

CPC分类号： H01L21/28194 ,  C23C16/45563 ,  C23C16/4558 ,  H01L29/513 ,  H01L29/517

摘要： A dispenser system for use in atomic beam assisted metal organic chemical vapor deposition is provided as well as a method of depositing an ultra-thin film using the same. The inventive dispenser system includes an atomic source having an unimpeded line of site to a substrate and an annular metal organic chemical vapor deposition showerhead having a plurality of nozzles for delivering a precursor to the substrate. In accordance with the present invention, each of the nozzles present on the showerhead is angled to provide precursor beam trajectories that crossover and are non-intercepting.

摘要翻译： 提供了用于原子束辅助金属有机化学气相沉积的分配器系统以及使用其分离超薄膜的方法。 本发明的分配器系统包括具有对衬底的无阻碍位置线的原子源和具有用于将前体输送到衬底的多个喷嘴的环形金属有机化学气相沉积喷头。 根据本发明，存在于喷头上的每个喷嘴都是成角度的，以提供跨越并且不被拦截的前体梁轨迹。

公开(公告)号：US07488656B2

公开(公告)日：2009-02-10

申请号：US11119310

申请日：2005-04-29

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Fenton R. McFeely ,  Vijay Narayanan

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Fenton R. McFeely ,  Vijay Narayanan

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/31691 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for removing charged defects from a material stack including a high k gate dielectric and a metal contact such that the final gate stack, which is useful in forming a pFET device, has a threshold voltage substantially within the silicon band gap and good carrier mobility. Specifically, the present invention provides a re-oxidation procedure that will restore the high k dielectric of a pFET device to its initial, low-defect state. It was unexpectedly determined that by exposing a material stack including a high k gate dielectric and a metal to dilute oxygen at low temperatures will substantially eliminate oxygen vacancies, resorting the device threshold to its proper value. Furthermore, it was determined that if dilute oxygen is used, it is possible to avoid undue oxidation of the underlying semiconductor substrate which would have a deleterious effect on the capacitance of the final metal-containing gate stack. The present invention also provides a semiconductor structure that includes at least one gate stack that has a threshold voltage within a control range and has good carrier mobility.

摘要翻译： 本发明提供了一种用于从包括高k栅极电介质和金属接触的材料堆叠中去除带电缺陷的方法，使得用于形成pFET器件的最终栅极堆叠具有基本上在硅带隙内的阈值电压 和良好的载波移动性。 具体地说，本发明提供了将pFET器件的高k电介质恢复到其初始低缺陷状态的再氧化过程。 意外地确定，通过暴露包括高k栅极电介质和金属的材料堆以在低温下稀释氧将基本上消除氧空位，使装置阈值达到适当的值。 此外，确定如果使用稀释氧，则可以避免对最终含金属的栅极叠层的电容产生有害影响的下面的半导体衬底的不适当的氧化。 本发明还提供一种半导体结构，该半导体结构包括至少一个栅极堆叠，其具有在控制范围内的阈值电压并具有良好的载流子迁移率。

公开(公告)号：US07067422B2

公开(公告)日：2006-06-27

申请号：US10830804

申请日：2004-03-31

申请人： Kazuhito Nakamura ,  Hideaki Yamasaki ,  Yumiko Kawano ,  Gert J. Leusink ,  Fenton R. McFeely ,  John J. Yurkas ,  Vijay Narayanan

发明人： Kazuhito Nakamura ,  Hideaki Yamasaki ,  Yumiko Kawano ,  Gert J. Leusink ,  Fenton R. McFeely ,  John J. Yurkas ,  Vijay Narayanan

IPC分类号： H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517

摘要： A method for forming a tantalum-containing gate electrode structure by providing a substrate having a high-k dielectric layer thereon in a process chamber and forming a tantalum-containing layer on the high-k dielectric layer in a thermal chemical vapor deposition process by exposing the substrate to a process gas containing TAIMATA (Ta(N(CH3)2)3(NC(C2H5)(CH3)2)) precursor gas. In one embodiment of the invention, the tantalum-containing layer can include a TaSiN layer formed from a process gas containing TAIMATA precursor gas, a silicon containing gas, and optionally a nitrogen-containing gas. In another embodiment of the invention, a TaN layer is formed on the TaSiN layer. The TaN layer can be formed from a process gas containing TAIMATA precursor gas and optionally a nitrogen-containing gas. A computer readable medium executable by a processor to cause a processing system to perform the method and a processing system for forming a tantalum-containing gate electrode structure are also provided.

摘要翻译： 一种通过在处理室中提供具有高k电介质层的衬底并在热化学气相沉积工艺中在高k电介质层上形成含钽层的方法来形成含钽栅电极结构的方法， 将衬底加工成含有TAIMATA（Ta（N（CH 3）2）3）（NC（C 2）2）的工艺气体， （CH 3）2））前体气体。 在本发明的一个实施方案中，含钽层可以包括由含有TAIMATA前体气体，含硅气体和任选的含氮气体的工艺气体形成的TaSiN层。 在本发明的另一实施例中，在TaSiN层上形成TaN层。 TaN层可以由含有TAIMATA前体气体和任选的含氮气体的工艺气体形成。 还提供了可由处理器执行以使处理系统执行该方法的计算机可读介质和用于形成含钽栅电极结构的处理系统。

公开(公告)号：US07749802B2

公开(公告)日：2010-07-06

申请号：US11621365

申请日：2007-01-09

申请人： Fenton R. McFeely ,  Alejandro G. Schrott ,  John J. Yurkas

发明人： Fenton R. McFeely ,  Alejandro G. Schrott ,  John J. Yurkas

IPC分类号： H01L21/00 ,  H01L21/82 ,  H01L21/20

CPC分类号： C23C16/30 ,  H01L21/28556 ,  H01L21/76877 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1683 ,  Y10T428/249994

摘要： A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials.

摘要翻译： 提供了一种用于沉积包括锗（Ge）和锑（Sb）在内的材料的化学气相沉积（CVD）方法，其在一些实施例中具有填充高纵横比开口的能力。 本发明的CVD方法允许在宽范围的值范围内控制GeSb化学计量，并且本发明的方法在低于400℃的衬底温度下进行，这使得本发明的方法与现有的互连工艺和材料兼容 。 除了上述之外，本发明的方法是非选择性CVD工艺，这意味着GeSb材料在绝缘和非绝缘材料上同样良好地沉积。