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公开(公告)号：US20210202502A1
公开(公告)日：2021-07-01
申请号：US16727673
申请日：2019-12-26
发明人： Fu-Chen CHANG , Kuo-Chi TU , Tzu-Yu CHEN , Sheng-Hung SHIH
IPC分类号： H01L27/1159 , G11C11/22 , H01L27/11587
摘要： A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.
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公开(公告)号：US20190103493A1
公开(公告)日：2019-04-04
申请号：US16207081
申请日：2018-11-30
发明人： Kuo-Chi TU , Jen-Sheng YANG , Sheng-Hung SHIH , Tong-Chern ONG , Wen-Ting CHU
IPC分类号： H01L29/78 , H01L29/51 , H01L29/66 , G11C11/22 , H01L27/1159 , H01L27/11592
摘要： A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
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公开(公告)号：US20180351099A1
公开(公告)日：2018-12-06
申请号：US15663671
申请日：2017-07-28
发明人： Jen-Sheng YANG , Wen-Ting CHU , Chih-Yang CHANG , Chin-Chieh YANG , Kuo-Chi TU , Sheng-Hung SHIH , Yu-Wen LIAO , Hsia-Wei CHEN , I-Ching CHEN
CPC分类号： H01L45/1675 , H01L21/76802 , H01L21/76819 , H01L21/76832 , H01L21/76835 , H01L21/76837 , H01L23/5226 , H01L23/5283 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/1616
摘要： A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.
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公开(公告)号：US20190164602A1
公开(公告)日：2019-05-30
申请号：US15870620
申请日：2018-01-12
发明人： Kuo-Chi TU , Chu-Jie HUANG , Sheng-Hung SHIH , Nai-Chao SU , Wen-Ting CHU
摘要： A memory device includes a bottom electrode, a resistance switching layer and a top electrode. The bottom electrode is over a metallization layer embedded in an inter-metal dielectric layer. The bottom electrode has a top surface and a sidewall that extends at an obtuse angle relative to the top surface. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.
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公开(公告)号：US20150092471A1
公开(公告)日：2015-04-02
申请号：US14041916
申请日：2013-09-30
发明人： Wen-Chun YOU , Kuo-Chi TU , Chih-Yang CHANG , Hsia-Wei CHEN , Yu-Wen LIAO , Chin-Chieh YANG , Sheng-Hung SHIH , Wen-Ting CHU
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/79
摘要： A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.
摘要翻译： 公开了一种包括以下概述的操作的方法。 在复位操作期间，第一电压被施加到每行存储单元的存取晶体管的栅极，其中存取晶体管的第一源极/漏极电连接到电阻随机存取存储器（RRAM）的第一电极 ）设备在同一个存储单元中。 当第一电压被施加到存取晶体管的栅极时，抑制电压被施加到RRAM器件的第二电极或多个未选择存储器单元中的每一个的存取晶体管的第二源极/漏极。
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公开(公告)号：US20240074206A1
公开(公告)日：2024-02-29
申请号：US18501360
申请日：2023-11-03
发明人： Fu-Chen CHANG , Kuo-Chi TU , Tzu-Yu CHEN , Sheng-Hung SHIH
摘要： A semiconductor device includes a random access memory (RAM) structure and a dielectric layer. The RAM structure is over a substrate and includes a bottom electrode layer, a ferroelectric layer over the bottom electrode layer, and a top electrode layer over the ferroelectric layer. The dielectric layer is over the substrate and laterally surrounds a lower portion of the RAM structure. From a cross-sectional view, the bottom electrode layer of the RAM structure has a lateral portion and a vertical portion, and the vertical portion upwardly extends from the lateral portion to a position higher than a top surface of the dielectric layer.
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公开(公告)号：US20180151746A1
公开(公告)日：2018-05-31
申请号：US15640127
申请日：2017-06-30
发明人： Kuo-Chi Tu , Jen-Sheng YANG , Sheng-Hung SHIH , Tong-Chern ONG , Wen-Ting CHU
IPC分类号： H01L29/78 , H01L27/1159 , H01L27/11592 , H01L29/51 , H01L29/66 , G11C11/22
CPC分类号： H01L29/78391 , G11C11/223 , G11C11/2257 , G11C11/2273 , H01L27/1159 , H01L27/11592 , H01L29/513 , H01L29/516 , H01L29/66545 , H01L29/6684
摘要： A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
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公开(公告)号：US20220231033A1
公开(公告)日：2022-07-21
申请号：US17712543
申请日：2022-04-04
发明人： Fu-Chen CHANG , Kuo-Chi TU , Tzu-Yu CHEN , Sheng-Hung SHIH
IPC分类号： H01L27/1159 , H01L27/11587 , G11C11/22 , H01L49/02 , H01L27/11507 , H01L27/11502
摘要： A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.
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公开(公告)号：US20210082928A1
公开(公告)日：2021-03-18
申请号：US16569487
申请日：2019-09-12
发明人： Tzu-Yu CHEN , Sheng-Hung SHIH , Kuo-Chi TU , Wen-Ting CHU
IPC分类号： H01L27/1159 , H01L23/522
摘要： A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.
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