公开(公告)号：US20250068811A1

公开(公告)日：2025-02-27

申请号：US18454267

申请日：2023-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Fang Chen ,  Ang-Chih Hsieh ,  Wei-Heng Lo ,  Heng-Yi Lin ,  Chih-Wei Chang

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/398

Abstract: An integrated circuit design implementation system includes a synthesis tool configured to: receive a behavioral description of each of a plurality of first components; generate first netlists based on the behavioral descriptions of the first components; receive connection information of a plurality of second components, wherein the connection information comprises physical arrangement and connectivity among the first components and the second components; generate a plurality of third components, wherein each of the third components operatively corresponds to an interface between a pair of one of the first components and one of the second components; and transform the first netlists to a second netlist based on first vertices, second vertices, third vertices, and edges. The first vertices correspond to the first components, respectively, the second vertices correspond to the second components, respectively, and the third vertices correspond to the third components, respectively.

公开(公告)号：US20240429102A1

公开(公告)日：2024-12-26

申请号：US18338715

申请日：2023-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Yip LOH ,  Hung-Hsu Chen ,  Chih-Chien Chi ,  Harry Chien ,  Chih-Wei Chang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes forming a bottom-tier transistor and a top-tier transistor over the bottom-tier transistor, the top-tier transistor comprising a first channel layer, a first gate structure around the first channel layer, and a plurality of first source/drain regions on opposite sides of the first channel layer; forming a first dielectric layer over the first source/drain regions of the top-tier transistor; etching the first dielectric layer to form a first opening exposing one of the first source/drain regions of the top-tier transistor; selectively forming a first metal silicide on the one of the first source/drain regions; selectively forming a first metal cap on the first metal silicide and not on the first dielectric layer; forming a front-side contact on the first metal cap.

公开(公告)号：US20230402278A1

公开(公告)日：2023-12-14

申请号：US17838253

申请日：2022-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Ming Tsai ,  Wei-Yip Loh ,  Harry CHIEN ,  Chih-Shiun Chou ,  Hong-Mao Lee ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/02

CPC classification number: H01L21/02123 ,  H01L21/02293 ,  H01L21/02381

Abstract: A method of forming a semiconductor device includes following operations. A substrate is provided with a gate stack thereon, an epitaxial layer therein, and a dielectric layer aside the gate stack and over the epitaxial layer. An opening is formed through the dielectric layer, and the opening exposes the epitaxial layer. A metal silicon-germanide layer is formed on the epitaxial layer, wherein the metal silicon-germanide layer includes a metal having a melting point of about 1700° C. or higher. A connector is formed over the metal silicon-germanide layer in the opening.

公开(公告)号：US20230117009A1

公开(公告)日：2023-04-20

申请号：US17669652

申请日：2022-02-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Yi Lin ,  Fong-yuan Chang ,  Po-Yu Chen ,  Po-Hsiang Huang ,  Chih-Wei Chang ,  Jyh Chwen Frank Lee

IPC: G06F30/392

Abstract: A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

公开(公告)号：US11309217B2

公开(公告)日：2022-04-19

申请号：US15909682

申请日：2018-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ya-Huei Li ,  Li-Wei Chu ,  Yu-Hsiang Liao ,  Hung-Yi Huang ,  Chih-Wei Chang ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321

Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.

公开(公告)号：US11227084B2

公开(公告)日：2022-01-18

申请号：US16522586

申请日：2019-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jerry Chang Jui Kao ,  Hui-Zhong Zhuang ,  Yung-Chen Chien ,  Ting-Wei Chiang ,  Chih-Wei Chang ,  Xiangdong Chen

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327 ,  H01L25/00 ,  H03K19/00

Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.

公开(公告)号：US11177172B2

公开(公告)日：2021-11-16

申请号：US16685948

申请日：2019-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yan-Ming Tsai ,  Wei-Yip Loh ,  Yu-Ming Huang ,  Hung-Hsu Chen ,  Chih-Wei Chang

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/535 ,  H01L29/165 ,  H01L29/78 ,  H01L29/45 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a source/drain structure disposed in the substrate at two sides of the gate structure, and a conductive plug. The source/drain structure includes an epitaxial layer and a dual metal silicide on the epitaxial layer. The epitaxial layer includes a first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. The dual metal silicide includes the first semiconductor material, the second semiconductor material, a first metal material and a second metal material. An atomic size of the second metal material is greater than an atomic size of the first metal material. The conductive plug penetrates the dual metal silicide.

公开(公告)号：US11101353B2

公开(公告)日：2021-08-24

申请号：US16387043

申请日：2019-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hsien Huang ,  Chang-Ting Chung ,  Wei-Cheng Lin ,  Wei-Jung Lin ,  Chih-Wei Chang

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L21/311 ,  H01L21/285 ,  H01L21/321 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/08

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

公开(公告)号：US20210035868A1

公开(公告)日：2021-02-04

申请号：US16527350

申请日：2019-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Yip Loh ,  Yan-Ming Tsai ,  Hung-Hsu Chen ,  Chih-Wei Chang ,  Sheng-Hsuan Lin

IPC: H01L21/8238 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092 ,  H01L29/45

Abstract: A semiconductor device with multiple silicide regions is provided. In embodiments a first silicide precursor and a second silicide precursor are deposited on a source/drain region. A first silicide with a first phase is formed, and the second silicide precursor is insoluble within the first phase of the first silicide. The first phase of the first silicide is modified to a second phase of the first silicide, and the second silicide precursor being soluble within the second phase of the first silicide. A second silicide is formed with the second silicide precursor and the second phase of the first silicide.

公开(公告)号：US10825724B2

公开(公告)日：2020-11-03

申请号：US14262467

申请日：2014-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.