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    Monolithic reference architecture with burst mode support
    1.
    发明授权
    Monolithic reference architecture with burst mode support 有权

    公开(公告)号：US10054969B2

    公开(公告)日：2018-08-21

    申请号：US15259368

    申请日：2016-09-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Anand Subramanian ,  Anand Kannan ,  Sunil Rafeeque ,  Venakatesh Guduri

    IPC: G05F1/10 ,  G05F3/02 ,  G05F1/565 ,  G05F1/625 ,  G05F3/16 ,  G05F1/575

    CPC classification number: G05F1/575

    Abstract: A reference circuit may include a bandgap reference stage, a filter stage, and a buffer stage. The reference stage may be configured to generate a reference voltage or current. The filter stage may be coupled to the reference stage and may be configured to receive the reference voltage or current, filter noise from the reference voltage or current, receive a buffer output voltage or current, and filter noise from the buffer output voltage or current. The buffer stage may be coupled to the filter stage and may be configured to isolate the reference stage and the filter stage from a loading effect of a load circuit and generate a reference signal based on the reference voltage or current to drive the load circuit.

    NOVEL TECHNIQUE TO COMBINE A COARSE ADC AND A SAR ADC
    2.
    发明申请
    NOVEL TECHNIQUE TO COMBINE A COARSE ADC AND A SAR ADC 有权
    合并ADC和ADC的新技术

    公开(公告)号：US20150188561A1

    公开(公告)日：2015-07-02

    申请号：US14255269

    申请日：2014-04-17

    Applicant: Texas Instruments Incorporated

    Inventor： Subramanian Jagdish Narayan ,  Anand Kannan

    IPC: H03M1/38 ,  H03M1/66 ,  H03M1/06

    CPC classification number: H03M1/144 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

    Abstract: A successive approximation register analog to digital converter (SAR ADC) is disclosed. The SAR ADC receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.

    Abstract translation: 公开了逐次逼近寄存器模数转换器（SAR ADC）。 SAR ADC接收输入电压和多个参考电压。 SAR ADC包含一个电荷共享DAC。 电荷共享DAC包括一个MSB（最高有效位）电容器阵列和一个LSB​​（最低有效位）电容器阵列。 零交叉检测器耦合到电荷共享DAC。 过零检测器产生数字输出。 粗略的ADC（模数转换器）接收输入电压并产生粗略的输出。 将预定义的偏移量添加到粗略ADC的残差。 逐次逼近寄存器（SAR）状态机耦合到粗略ADC和过零检测器，并产生多个控制信号。 多个控制信号以采样模式，纠错模式和转换模式操作电荷共享DAC。

    Piecewise correction of errors over temperature without using on-chip temperature sensor/comparators
    3.
    发明授权
    Piecewise correction of errors over temperature without using on-chip temperature sensor/comparators 有权

    公开(公告)号：US11409317B2

    公开(公告)日：2022-08-09

    申请号：US15962515

    申请日：2018-04-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Praful Kumar Parakh ,  Anand Kannan ,  Sunil Rafeeque

    IPC: G05F3/24

    Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

    Piecewise correction of errors over temperature without using on-chip temperature sensor/comparators
    4.
    发明授权
    Piecewise correction of errors over temperature without using on-chip temperature sensor/comparators 有权

    公开(公告)号：US09971375B2

    公开(公告)日：2018-05-15

    申请号：US14949390

    申请日：2015-11-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Praful Kumar Parakh ,  Anand Kannan ,  Sunil Rafeeque

    IPC: G05F3/24

    CPC classification number: G05F3/245

    Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

    ANALOG-TO-DIGITAL CONVERTER WITH INSTABILITY RECOVERY CIRCUIT
    5.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER WITH INSTABILITY RECOVERY CIRCUIT 有权

    公开(公告)号：US20250030429A1

    公开(公告)日：2025-01-23

    申请号：US18591676

    申请日：2024-02-29

    Applicant: Texas Instruments Incorporated

    Inventor： Jyoti Raj ,  Anand Subramanian ,  Anand Kannan

    IPC: H03M1/06

    Abstract: In described examples, an integrated circuit (IC) includes first and second integrators, first and second weighted summers, first and second digital-to-analog converters (DACs), and a quantizer. First and second inputs of the first weighted summer are respectively connected to an output of the first integrator and an output of the second DAC. An input of the second integrator is connected to an output of the first weighted summer. An input of the second weighted summer is connected to an output of the second integrator. An input of the quantizer is connected to an output of the second weighted summer. Inputs of the first and second DACs are connected to respective outputs of the quantizer. An output of the first DAC is connected to a first input of the first integrator. A second input of the first integrator and a third input of the first weighted summer are analog signal inputs.

    Piecewise Correction of Errors Over Temperature without Using On-Chip Temperature Sensor/Comparators
    6.
    发明申请
    Piecewise Correction of Errors Over Temperature without Using On-Chip Temperature Sensor/Comparators 有权

    公开(公告)号：US20220350360A1

    公开(公告)日：2022-11-03

    申请号：US17868684

    申请日：2022-07-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Praful Kumar Parakh ,  Anand Kannan ,  Sunil Rafeeque

    IPC: G05F3/24

    Abstract: A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

    Adding predefined offset to coarse ADC residue output to SAR
    7.
    发明授权
    Adding predefined offset to coarse ADC residue output to SAR 有权
    将预定义的偏移量添加到粗略的ADC残差输出到SAR

    公开(公告)号：US09148166B2

    公开(公告)日：2015-09-29

    申请号：US14255269

    申请日：2014-04-17

    Applicant: Texas Instruments Incorporated

    Inventor： Subramanian Jagdish Narayan ,  Anand Kannan

    IPC: H03M1/06 ,  H03M1/38 ,  H03M1/66

    CPC classification number: H03M1/144 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

    Abstract: A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.

    Abstract translation: 逐次逼近寄存器模数转换器（SAR ADC）接收输入电压和多个参考电压。 SAR ADC包含一个电荷共享DAC。 电荷共享DAC包括一个MSB（最高有效位）电容器阵列和一个LSB​​（最低有效位）电容器阵列。 零交叉检测器耦合到电荷共享DAC。 过零检测器产生数字输出。 粗略的ADC（模数转换器）接收输入电压并产生粗略的输出。 将预定义的偏移量添加到粗略ADC的残差。 逐次逼近寄存器（SAR）状态机耦合到粗略ADC和过零检测器，并产生多个控制信号。 多个控制信号以采样模式，纠错模式和转换模式操作电荷共享DAC。

    Low power excess loop delay compensation technique for delta-sigma modulators
    8.
    发明授权
    Low power excess loop delay compensation technique for delta-sigma modulators 有权
    用于Δ-Σ调制器的低功率多余环路延迟补偿技术

    公开(公告)号：US09118342B2

    公开(公告)日：2015-08-25

    申请号：US14033047

    申请日：2013-09-20

    Applicant: Texas Instruments Incorporated

    Inventor： Vikas Singh ,  Anand Kannan ,  Ashish Lachhwani

    IPC: H03M3/00 ,  H03M1/00 ,  H03M1/46

    CPC classification number: H03M3/372 ,  H03M1/002 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/454

    Abstract: A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.

    Abstract translation: 具有输入级和输出级的Δ-Σ调制器。 输入级接收模拟输入信号和第一数模转换器（DAC）的输出。 输入级产生处理后的误差信号。 附加求和装置接收处理的误差信号。 输出级接收附加求和装置的输出并产生延迟的数字输出信号。 差分器和第一个数模转换器（DAC）接收延迟的数字输出信号作为反馈信号。 第二DAC接收微分器的输出，并向另外的负反馈系数乘法器提供输出。 附加求和装置接收附加负反馈系数乘法器的输出。

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