公开(公告)号：US20230326002A1

公开(公告)日：2023-10-12

申请号：US18333151

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY, JR. ,  Veeramanikandan RAJU ,  Niraj NANDAN ,  Samuel Paul VISALLI ,  Jason A.T. JONES ,  Kedar Satish CHITNIS ,  Gregory Raymond SHURTZ ,  Prithvi Shankar YEYYADI ANANTHA ,  Sriramakrishnan GOVINDARAJAN

IPC: G06T7/00 ,  G06T1/20 ,  G06T3/40 ,  G05B23/02

CPC classification number: G06T7/0002 ,  G06T1/20 ,  G06T3/40 ,  H04N17/00 ,  G06T7/97 ,  G06T2207/10016 ,  G05B23/0259

Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.

公开(公告)号：US20230267084A1

公开(公告)日：2023-08-24

申请号：US17677638

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY, JR. ,  Ankur ANKUR ,  Vivek Vilas DHANDE ,  Kedar Satish CHITNIS ,  Niraj NANDAN ,  Brijesh JADAV ,  Shyam JAGANNATHAN ,  Prithvi Shankar YEYYADI ANANTHA ,  Santhanakrishnan Narayanan NARAYANAN

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78 ,  G06F9/48

CPC classification number: G06F13/28 ,  G06F13/1673 ,  G06F13/4221 ,  G06F15/7807 ,  G06F9/4881

Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.