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    ADAPTIVE MODULATION SYSTEM AND METHOD TO MINIMIZE ENERGY CONSUMPTION
    3.
    发明申请
    ADAPTIVE MODULATION SYSTEM AND METHOD TO MINIMIZE ENERGY CONSUMPTION 有权
    自适应调节系统和最小化能源消耗的方法

    公开(公告)号：US20150358050A1

    公开(公告)日：2015-12-10

    申请号：US14586867

    申请日：2014-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Srinivas Lingam ,  Tarkesh Pande

    IPC: H04B3/54

    CPC classification number: H04B3/544 ,  H04B3/542

    Abstract: A communication device includes a modulating component, a transmitting component and a controlling component. The modulating component generates a first modulated packet and a second modulated packet. The first modulated packet is based on a first modulation scheme and the second modulated packet is based on a second modulation scheme. The first modulation scheme has a first amount of energy associated therewith, and the second modulation scheme has a second amount of energy associated therewith. The first amount of energy is less than the second amount of energy. The transmitting component generates a transmit packet based on one of the first modulated packet and the second modulated packet. The controlling component generates a control signal to instruct the modulating component to generate the first modulated packet When the transmit packet will be less than a predetermined threshold. The threshold is based on the first amount of energy.

    Abstract translation: 通信装置包括调制部件，发送部件和控制部件。 调制组件产生第一调制分组和第二调制分组。 第一调制分组基于第一调制方案，第二调制分组基于第二调制方案。 第一调制方案具有与之相关联的第一量的能量，并且第二调制方案具有与其相关联的第二量的能量。 第一能量量小于第二能量。 发送组件基于第一调制分组和第二调制分组中的一个生成发送分组。 当发送分组将小于预定阈值时，控制分量产生控制信号以指示调制分量生成第一调制分组。 阈值基于第一能量量。

    OUTPUT RANGE FOR INTERPOLATION ARCHITECTURES EMPLOYING A CASCADED INTEGRATOR-COMB (CIC) FILTER WITH A MULTIPLIER
    4.
    发明申请
    OUTPUT RANGE FOR INTERPOLATION ARCHITECTURES EMPLOYING A CASCADED INTEGRATOR-COMB (CIC) FILTER WITH A MULTIPLIER 有权
    使用带有乘法器的CASCADED INTEGRATOR-COMB（CIC）过滤器的插值结构的输出范围

    公开(公告)号：US20150236670A1

    公开(公告)日：2015-08-20

    申请号：US14624218

    申请日：2015-02-17

    Applicant: Texas Instruments Incorporated

    Inventor： Tarkesh Pande ,  Srinivas Lingam

    IPC: H03H17/02

    CPC classification number: H03H17/0671

    Abstract: A cascaded integrator-comb filter (CIC) that includes a differentiator, a rate changer, an integrator, and a multiplier. The differentiator is configured to differentiate an input signal to produce a differentiated input signal. The rate changer is coupled to the differentiator and is configured to interpolate the differentiated input signal based on an interpolation rate to produce an upsample signal. The integrator is coupled to the rate changer and is configured to integrate the upsample signal to produce an output signal. The multiplier is coupled to the differentiator, rate changer, and integrator and is configured to increase the output signal amplitude based on the interpolation rate.

    Abstract translation: 包括微分器，变换器，积分器和乘法器的级联积分器梳状滤波器（CIC）。 微分器被配置为区分输入信号以产生微分输入信号。 速率变换器耦合到微分器，并且被配置为基于插值速率内插差分输入信号以产生上采样信号。 积分器耦合到速率变换器，并被配置为集成上采样信号以产生输出信号。 乘法器耦合到微分器，变换器和积分器，并且被配置为基于插值速率来增加输出信号幅度。

    Gas volume determination in fluid
    5.
    发明授权
    Gas volume determination in fluid 有权

    公开(公告)号：US12196587B2

    公开(公告)日：2025-01-14

    申请号：US18449463

    申请日：2023-08-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Anand Dabak ,  Srinivas Lingam

    IPC: G01F1/66 ,  G01F1/667 ,  G01F1/7082 ,  G01N29/02 ,  G01N29/024 ,  G01N29/36 ,  G01N29/44 ,  G01F1/712 ,  G01F1/74

    Abstract: An integrated circuit includes one or more central processing unit (CPU) cores configured to cause a first ultrasonic transducer to generate ultrasonic signals into a fluid moving in a pipe and the first or a second ultrasonic transducer to receive the ultrasonic signals from the fluid. The CPU core(s) also compute a first value indicative of at least one of a standard deviation and a time correlation based on the received ultrasonic signals. The CPU core(s) further determine a second value indicative of a volume of gas bubbles in the fluid using the computed first value indicative of the at least one of the standard deviation and time correlation.

    Low energy accelerator processor architecture with short parallel instruction word
    7.
    发明授权
    Low energy accelerator processor architecture with short parallel instruction word 有权

    公开(公告)号：US10740280B2

    公开(公告)日：2020-08-11

    申请号：US15714212

    申请日：2017-09-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

    IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

    Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

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