公开(公告)号：US20230378961A1

公开(公告)日：2023-11-23

申请号：US18115682

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Bhavesh G. Bhakta ,  Venkateswara Reddy Pothireddy ,  Abhijit Kumar Das

IPC: H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0818 ,  H03L7/0816 ,  H03L7/0814 ,  H03L7/085

Abstract: An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.

公开(公告)号：US20240313786A1

公开(公告)日：2024-09-19

申请号：US18678824

申请日：2024-05-30

Applicant: Texas Instruments Incorporated

Inventor： Bhavesh G. Bhakta ,  Venkateswara Reddy Pothireddy ,  Abhijit Kumar Das

IPC: H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0818 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

Abstract: An example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (DLL) circuitry having a first DLL terminal and a second DLL terminal, the first DLL terminal coupled to the first controller terminal. The system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second DLL terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second DLL terminal and the fifth retimer terminal coupled to the third controller terminal.

公开(公告)号：US10574235B2

公开(公告)日：2020-02-25

申请号：US16284212

申请日：2019-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K19/0175 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US20230223903A1

公开(公告)日：2023-07-13

申请号：US18188064

申请日：2023-03-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswara Reddy Pothireddy

IPC: G05F3/20 ,  G05F1/46 ,  G05F3/26

CPC classification number: G05F3/205 ,  G05F1/468 ,  G05F3/262

Abstract: Systems and circuits include an amplifier having an output; a switching circuit coupled to the output of the amplifier to provide a bias current to bias the amplifier; first current generating circuitry coupled to the switching circuit; and second current generating circuitry coupled to the output of the amplifier and to the switching circuit. In operation, the switching circuit provides the bias current, during a first time period, in response to a first signal generated by the first current generating circuitry, and provides the bias current, during a second time period, after the first time period, in response to a second signal generated by the second current generating circuitry.

公开(公告)号：US20180241378A1

公开(公告)日：2018-08-23

申请号：US15437593

申请日：2017-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K3/037

CPC classification number: H03K19/017509 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US12289114B2

公开(公告)日：2025-04-29

申请号：US18678824

申请日：2024-05-30

Applicant: Texas Instruments Incorporated

Inventor： Bhavesh G. Bhakta ,  Venkateswara Reddy Pothireddy ,  Abhijit Kumar Das

IPC: H03L7/081 ,  H03L7/085

Abstract: An example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (DLL) circuitry having a first DLL terminal and a second DLL terminal, the first DLL terminal coupled to the first controller terminal. The system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second DLL terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second DLL terminal and the fifth retimer terminal coupled to the third controller terminal.

公开(公告)号：US12040752B2

公开(公告)日：2024-07-16

申请号：US18188064

申请日：2023-03-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswara Reddy Pothireddy

IPC: H03F1/30 ,  G05F1/46 ,  G05F3/20 ,  G05F3/26

CPC classification number: H03F1/301 ,  G05F1/468 ,  G05F3/205 ,  G05F3/262 ,  H03F2200/447

Abstract: Systems and circuits include an amplifier having an output; a switching circuit coupled to the output of the amplifier to provide a bias current to bias the amplifier; first current generating circuitry coupled to the switching circuit; and second current generating circuitry coupled to the output of the amplifier and to the switching circuit. In operation, the switching circuit provides the bias current, during a first time period, in response to a first signal generated by the first current generating circuitry, and provides the bias current, during a second time period, after the first time period, in response to a second signal generated by the second current generating circuitry.

公开(公告)号：US12028079B2

公开(公告)日：2024-07-02

申请号：US18115682

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Bhavesh G. Bhakta ,  Venkateswara Reddy Pothireddy ,  Abhijit Kumar Das

IPC: H03L7/081 ,  H03L7/085

CPC classification number: H03L7/0818 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

Abstract: An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.

公开(公告)号：US11637534B2

公开(公告)日：2023-04-25

申请号：US17592305

申请日：2022-02-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswara Reddy Pothireddy

IPC: H03F1/30 ,  G05F3/26

Abstract: In an example, a system includes an amplifier configured to produce a bandgap voltage reference. The system also includes a current source configured to provide a current to bias the amplifier. The system includes a switching circuit configured to receive a first current replica signal and a second current replica signal, the switching circuit further configured to cause the current source to provide the current to bias the amplifier based on either the first current replica signal or the second current replica signal.

公开(公告)号：US10541676B2

公开(公告)日：2020-01-21

申请号：US16057211

申请日：2018-08-07

Applicant: Texas Instruments Incorporated

Inventor： Venkateswara Reddy Pothireddy ,  Wahed Abdul Mohammed

IPC: H03K3/012 ,  H03K17/687 ,  H03K19/0185

Abstract: In a described example, an apparatus includes a driver circuit coupled to an output pad, the driver having a p-channel FET coupled between a positive peripheral voltage and the pad, and having a first gate terminal coupled to a first gate control signal, and an n-channel FET coupled between the pad and a ground terminal and having a second gate terminal coupled to a second gate control signal. A predriver circuit is coupled to receive a data signal for output to the pad and further coupled to output the first gate control signal; and the predriver circuit is coupled to output a supply voltage to the first gate control signal in a first mode, and to output a bias voltage less than the supply voltage to the first gate control signal in a second mode; and a bias circuit is coupled for outputting the bias voltage.