公开(公告)号：US10804234B2

公开(公告)日：2020-10-13

申请号：US16382503

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Bor-Ping Jang ,  Hsiao-Chung Liang

IPC: H01L25/10 ,  H01L23/14 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.

公开(公告)号：US11139177B2

公开(公告)日：2021-10-05

申请号：US16896038

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L21/60 ,  H01L21/603 ,  H01L23/538

Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.

公开(公告)号：US10727074B2

公开(公告)日：2020-07-28

申请号：US14842337

申请日：2015-09-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien Ling Hwang ,  Bor-Ping Jang ,  Hsin-Hung Liao ,  Chung-Shi Liu

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/68 ,  H01L21/67 ,  H01L21/78 ,  H01L21/683 ,  C23C16/458 ,  B05C21/00

Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly and securing an etching mask to a backside of the wafer. The etching mask covers a peripheral portion of the wafer. The method further includes performing a wet etching process on the backside of the wafer to form a thinned wafer, and the thinned wafer includes peripheral portions having a first thickness and a central portion having a second thickness smaller than the first thickness. A system for forming the thinned wafer is also provided.

公开(公告)号：US10276531B2

公开(公告)日：2019-04-30

申请号：US15596392

申请日：2017-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Bor-Ping Jang ,  Hsiao-Chung Liang

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48

Abstract: The present disclosure relates to a semiconductor device. In some embodiments, the semiconductor device has a first plurality of conductive pads arranged over a first substrate. A conductive solder material is arranged over and is electrically connected to the first plurality of conductive pads. A first boundary structure separates each conductive pad of the first plurality of conductive pads from an adjacent conductive pad of the first plurality of conductive pads. A die is arranged over the first substrate. The die has outermost sidewalls that are laterally separated from first and second ones of the first plurality of conductive pads by the first boundary structure.

公开(公告)号：US11233032B2

公开(公告)日：2022-01-25

申请号：US16703095

申请日：2019-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien-Ling Hwang ,  Bor-Ping Jang ,  Hsiao-Chung Liang ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L25/11 ,  H01L25/03

Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.

公开(公告)号：US11094561B2

公开(公告)日：2021-08-17

申请号：US16896039

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L21/60 ,  H01L21/603 ,  H01L23/538

Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

公开(公告)号：US10679866B2

公开(公告)日：2020-06-09

申请号：US14622484

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/60 ,  H01L21/603 ,  H01L23/538

Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.

公开(公告)号：US20190237422A1

公开(公告)日：2019-08-01

申请号：US16382503

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Bor-Ping Jang ,  Hsiao-Chung Liang

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/14

Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.

公开(公告)号：US11721555B2

公开(公告)日：2023-08-08

申请号：US16939470

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Hsin-Hung Liao ,  Chung-Shi Liu

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/68 ,  H01L21/67 ,  H01L21/78 ,  H01L21/683 ,  C23C16/458 ,  B05C21/00

CPC classification number: H01L21/3083 ,  H01L21/3081 ,  H01L21/30604 ,  H01L21/6708 ,  H01L21/682 ,  H01L21/6835 ,  H01L21/78 ,  B05C21/005 ,  C23C16/4585 ,  H01L21/6836 ,  H01L2221/6834 ,  H01L2221/68327

Abstract: A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly, and the support assembly includes a plurality of pin. The method includes securing an etching mask to a backside of the wafer, and the etching mask has an extending portion which covers a peripheral portion of the wafer. The etching mask has a plurality of circular bores extended along a vertical direction, and the etching mask is secured to the support assembly by connecting the circular bores and the pins. The method also includes performing a wet etching process on the backside of the wafer to foil a thinned wafer, wherein the thinned wafer has a peripheral portion with a first thickness and a central portion having a second thickness smaller than the first thickness.

公开(公告)号：US09768142B2

公开(公告)日：2017-09-19

申请号：US13944334

申请日：2013-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien Ling Hwang ,  Bor-Ping Jang ,  Hsiao-Chung Liang ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/03 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45147 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.