公开(公告)号：US10509883B2

公开(公告)日：2019-12-17

申请号：US15413551

申请日：2017-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsun-Yu Yang ,  Wei-Yi Hu ,  Jui-Feng Kuan ,  Hsien-Hsin Sean Lee ,  Po-Cheng Pan ,  Hung-Wen Huang ,  Hung-Ming Chen ,  Abhishek Patyal

IPC: G06F17/50 ,  G06F9/455

Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

公开(公告)号：US10340366B2

公开(公告)日：2019-07-02

申请号：US15653094

申请日：2017-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih Chieh Yeh ,  Chih-Sheng Chang ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US11776911B2

公开(公告)日：2023-10-03

申请号：US17330834

申请日：2021-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ming Chen ,  Yu-Chang Lin ,  Chung-Ting Li ,  Jen-Hsiang Lu ,  Hou-Ju Li ,  Chih-Pin Tsao

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L23/535 ,  H01L21/76841 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848

Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

公开(公告)号：US11024582B2

公开(公告)日：2021-06-01

申请号：US15489905

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ming Chen ,  Yu-Chang Lin ,  Chung-Ting Li ,  Jen-Hsiang Lu ,  Hou-Ju Li ,  Chih-Pin Tsao

IPC: H01L29/76 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417

Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

公开(公告)号：US20180301417A1

公开(公告)日：2018-10-18

申请号：US15489905

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ming Chen ,  Yu-Chang Lin ,  Chung-Ting Li ,  Jen-Hsiang Lu ,  Hou-Ju Li ,  Chih-Pin Tsao

IPC: H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

公开(公告)号：US11145750B2

公开(公告)日：2021-10-12

申请号：US16459529

申请日：2019-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih Chieh Yeh ,  Chih-Sheng Chang ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US09741829B2

公开(公告)日：2017-08-22

申请号：US14714227

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih Chieh Yeh ,  Chih-Sheng Chang ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

公开(公告)号：US11004709B2

公开(公告)日：2021-05-11

申请号：US16127919

申请日：2018-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chieh Hsieh ,  Su-Yu Yeh ,  Ko-Bin Kao ,  Chia-Hung Chung ,  Li-Jen Wu ,  Chun-Yu Chen ,  Hung-Ming Chen ,  Yong-Ting Wu

IPC: H01L21/67 ,  G01N33/00 ,  H01L21/673 ,  B05C15/00

Abstract: A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.

公开(公告)号：US09876117B2

公开(公告)日：2018-01-23

申请号：US15478758

申请日：2017-04-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih-Chieh Yeh ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/70 ,  H01L29/06 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/78 ,  H01L23/31 ,  H01L21/324 ,  H01L21/322 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7853 ,  H01L21/322 ,  H01L21/324 ,  H01L21/823431 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature. The passivation layer separates the fin structure from the interfacial layer.

公开(公告)号：US09660025B2

公开(公告)日：2017-05-23

申请号：US14840904

申请日：2015-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih-Chieh Yeh ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L21/70 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/06 ,  H01L29/66 ,  H01L21/322

CPC classification number: H01L29/7853 ,  H01L21/322 ,  H01L21/324 ,  H01L21/823431 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.