公开(公告)号：US20240413102A1

公开(公告)日：2024-12-12

申请号：US18462499

申请日：2023-09-07

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Hung-Pin Chang ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/58 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

Abstract: A method includes etching a portion of a wafer to form a first trench in a scribe line of the wafer, wherein the scribe line is between a first device die and a second device die of the wafer. After the etching, a top surface of the portion of wafer in the scribe line is underlying and exposed to the first trench, and the first trench is between opposing sidewalls of the wafer. A laser grooving process is then performed to form a second trench extending from the top surface further down into the wafer, and the second trench is laterally between the opposing sidewalls of the wafer. A die-saw process is then performed to saw the wafer. The die-saw process is performed from a bottom of the second trench, and the die-saw process results in the first device die to be separated from the second device die.

公开(公告)号：US20240413097A1

公开(公告)日：2024-12-12

申请号：US18451269

申请日：2023-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

Abstract: In an embodiment, a package include an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds. The package further includes an encapsulant over the interposer and surrounding the integrated circuit die. The encapsulant is further disposed between the first insulating bonding layer and the second insulating bonding layer along a line perpendicular to a major surface of the first semiconductor substrate.

公开(公告)号：US20240413101A1

公开(公告)日：2024-12-12

申请号：US18452257

申请日：2023-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/58 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: In an embodiment, a package includes an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer, a first seal ring, and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds, and wherein the integrated circuit die overlaps the first seal ring. A sidewall of the integrated circuit die is exposed at an outer sidewall of the package.

公开(公告)号：US20230402429A1

公开(公告)日：2023-12-14

申请号：US18151758

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Fu Tseng ,  Yu Chieh Yung ,  Cheng-Hsien Hsieh ,  Hung-Pin Chang ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L25/105 ,  H01L23/49833 ,  H01L23/481 ,  H01L21/486 ,  H01L23/5383 ,  H01L24/20 ,  H01L24/19 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/0557 ,  H01L2224/214 ,  H01L2224/19

Abstract: Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.

公开(公告)号：US20240421077A1

公开(公告)日：2024-12-19

申请号：US18506641

申请日：2023-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/58 ,  H01L25/065

Abstract: A package device for 3D stacking of integrated circuits includes a semiconductor substrate, and an interconnect structure on the semiconductor substrate. The interconnect structure is organized into a plurality of device regions, and the device has a first seal ring extending vertically through the interconnect structure in a first device region, and a second seal ring extending vertically through the interconnect structure in a second device region. The interconnect structure also includes a conductive line electrically connecting a metallization pattern within the first seal ring to a second metallization pattern within the second seal ring, wherein the first horizontally extending conductive line extends through the first seal ring and the second seal ring.

公开(公告)号：US20240071947A1

公开(公告)日：2024-02-29

申请号：US17823157

申请日：2022-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ling Tsai ,  Lai Wei Chih ,  Meng-Tsan Lee ,  Hung-Pin Chang ,  Li-Han Hsu ,  Chien-Chia Chiu ,  Cheng-Hung Lin

IPC: H01L23/00 ,  H01L23/053 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L23/053 ,  H01L25/18 ,  H01L24/24 ,  H01L24/97 ,  H01L2224/24225 ,  H01L2224/97

Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.

公开(公告)号：US20240421111A1

公开(公告)日：2024-12-19

申请号：US18506747

申请日：2023-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/00

Abstract: A package device includes a top die having a top interconnect structure on a first surface of a transistor layer and a bottom interconnect structure on a second surface of the transistor layer. One of the top interconnect structure or the bottom interconnect structure is direct bonded onto a bottom die. The bottom interconnect structure includes a power rail which directly contacts transistor contacts that are directly contacting a transistor structure in the transistor layer.