公开(公告)号：US12224247B2

公开(公告)日：2025-02-11

申请号：US18616427

申请日：2024-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31

Abstract: A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

公开(公告)号：US20240421077A1

公开(公告)日：2024-12-19

申请号：US18506641

申请日：2023-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Pin Chang ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/58 ,  H01L25/065

Abstract: A package device for 3D stacking of integrated circuits includes a semiconductor substrate, and an interconnect structure on the semiconductor substrate. The interconnect structure is organized into a plurality of device regions, and the device has a first seal ring extending vertically through the interconnect structure in a first device region, and a second seal ring extending vertically through the interconnect structure in a second device region. The interconnect structure also includes a conductive line electrically connecting a metallization pattern within the first seal ring to a second metallization pattern within the second seal ring, wherein the first horizontally extending conductive line extends through the first seal ring and the second seal ring.

公开(公告)号：US11967563B2

公开(公告)日：2024-04-23

申请号：US17402734

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Fu Lin ,  Chen-Hua Yu ,  Meng-Tsan Lee ,  Wei-Cheng Wu ,  Hsien-Wei Chen

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L23/5286 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L25/105 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/562 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/17181 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73101 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

公开(公告)号：US11901320B2

公开(公告)日：2024-02-13

申请号：US18064371

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chia Huang ,  Tsung-Shu Lin ,  Cheng-Chieh Hsieh ,  Wei-Cheng Wu

IPC: H01L21/76 ,  H01L21/56 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/31 ,  H01L21/683 ,  H01L25/10

CPC classification number: H01L24/06 ,  H01L21/565 ,  H01L21/76885 ,  H01L23/3185 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05015 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/06179 ,  H01L2224/06515 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81805 ,  H01L2224/83005 ,  H01L2224/838 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/2064 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/19 ,  H01L2224/83005 ,  H01L2224/18 ,  H01L2924/0001

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

公开(公告)号：US11682593B2

公开(公告)日：2023-06-20

申请号：US16932948

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Chen-Hua Yu ,  Hsien-Pin Hu ,  Tzu-Yu Wang ,  Wei-Cheng Wu ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC: H01L21/48 ,  H01L21/66 ,  H01L23/498 ,  G01R1/073 ,  H01L23/522 ,  H01L23/58 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L22/32 ,  G01R1/07378 ,  H01L21/486 ,  H01L21/4853 ,  H01L22/30 ,  H01L22/34 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/585 ,  H01L21/561 ,  H01L21/6835 ,  H01L2221/68331 ,  H01L2224/05001 ,  H01L2224/056 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2224/056 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

公开(公告)号：US11257816B2

公开(公告)日：2022-02-22

申请号：US16794044

申请日：2020-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/321

Abstract: A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.

公开(公告)号：US11195802B2

公开(公告)日：2021-12-07

申请号：US16893440

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC: H01L23/552 ,  H01L21/76 ,  H01L23/538 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US20210305122A1

公开(公告)日：2021-09-30

申请号：US16835322

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/52

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

公开(公告)号：US20210098391A1

公开(公告)日：2021-04-01

申请号：US16893440

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/488 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US10783954B2

公开(公告)日：2020-09-22

申请号：US15991739

申请日：2018-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng Wu ,  Chih-Yu Lin ,  Kao-Cheng Lin ,  Wei-Min Chan ,  Yen-Huei Chen

IPC: G11C11/419 ,  H01L27/11 ,  G11C11/413 ,  G11C11/412

Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.