公开(公告)号：US20250167161A1

公开(公告)日：2025-05-22

申请号：US18585854

申请日：2024-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jin Hu ,  Hua-Wei Tseng ,  Wei-Cheng Wu ,  Yung-Ping Chiang ,  An-Jhih Su ,  Der-Chyang Yeh

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: A package includes a first die over and bonded to a first side of a package component, where a first bond between the first die and the package component includes a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and second bonds between the first die and the package component include metal-to-metal bonds between first bonding pads of the first die and second bonding pads on the package component, a first portion of a redistribution structure adjacent to the first die and over the second bonding layer, and a second die over and coupled to the first portion of the redistribution structure using first conductive connectors, where the first conductive connectors are electrically connected to first conductive pads in the second bonding layer.

公开(公告)号：US11984405B2

公开(公告)日：2024-05-14

申请号：US17813102

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/105 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/06179 ,  H01L2224/13147 ,  H01L2224/16052 ,  H01L2224/16055 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17135 ,  H01L2224/17136 ,  H01L2224/17179 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/16052 ,  H01L2924/00012 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

公开(公告)号：US11961800B2

公开(公告)日：2024-04-16

申请号：US17814152

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L25/07 ,  H01L25/075 ,  H01L33/00 ,  H01L33/38 ,  H01L33/62 ,  H01L21/321 ,  H01L33/06 ,  H01L33/32

CPC classification number: H01L23/5226 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/11 ,  H01L24/89 ,  H01L25/072 ,  H01L25/0753 ,  H01L33/0093 ,  H01L33/38 ,  H01L33/62 ,  H01L21/3212 ,  H01L24/81 ,  H01L33/007 ,  H01L33/06 ,  H01L33/32 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/08225 ,  H01L2224/08501 ,  H01L2224/80006 ,  H01L2224/80815 ,  H01L2224/80895 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

公开(公告)号：US11804475B2

公开(公告)日：2023-10-31

申请号：US18175189

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/16 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80006 ,  H01L2224/80904 ,  H01L2224/9202 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US20230335534A1

公开(公告)日：2023-10-19

申请号：US17865969

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L25/50 ,  H01L24/97

Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die bonded to the first integrated circuit die in a face-to-back manner; a dummy semiconductor feature adjacent the second integrated circuit die and bonded to the first integrated circuit die; a support substrate attached to the dummy semiconductor feature and the second integrated circuit die; and a passivation layer extending along a top surface of the support substrate, an outer sidewall of the dummy semiconductor feature, an outer sidewall of the first integrated circuit die, and a top surface of the first integrated circuit die.

公开(公告)号：US11728249B2

公开(公告)日：2023-08-15

申请号：US17373063

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming Shih Yeh

IPC: H01L23/485 ,  H01L23/522 ,  H01L25/10 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/485 ,  H01L21/4857 ,  H01L21/4867 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/022 ,  H01L2224/04105 ,  H01L2224/0508 ,  H01L2224/05624 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

公开(公告)号：US20230245903A1

公开(公告)日：2023-08-03

申请号：US18297897

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Wei-Yu Chen

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L25/18 ,  H01L21/683 ,  H01L23/498

CPC classification number: H01L21/568 ,  H01L24/28 ,  H01L23/49503 ,  H01L25/18 ,  H01L24/19 ,  H01L24/20 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

公开(公告)号：US11682654B2

公开(公告)日：2023-06-20

申请号：US16718073

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Li-Hsien Huang ,  Ta-Hsuan Lin ,  Ming-Shih Yeh

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827

Abstract: A semiconductor structure includes a semiconductor structure includes a semiconductor die, an insulating encapsulation, a passivation layer and conductive elements. The semiconductor die includes a sensor device and a semiconductor substrate with a first region and a second region adjacent to the first region, and the sensor device is embedded in the semiconductor substrate within the first region. The insulating encapsulation laterally encapsulates the semiconductor die and covers a sidewall of the semiconductor die. The passivation layer is located on the semiconductor die, wherein a recess penetrates through the passivation layer over the first region and is overlapped with the sensor device. The conductive elements are located on the passivation layer over the second region and are electrically connected to the semiconductor die, wherein the passivation layer is between the insulating encapsulation and the conductive elements.

公开(公告)号：US11652063B2

公开(公告)日：2023-05-16

申请号：US16927126

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Tsung-Shu Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73253 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

公开(公告)号：US11508695B2

公开(公告)日：2022-11-22

申请号：US17195903

申请日：2021-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.