公开(公告)号：US20250105090A1

公开(公告)日：2025-03-27

申请号：US18974937

申请日：2024-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chia Chiu ,  Li-Han Hsu

IPC: H01L23/40 ,  H01L23/04 ,  H01L23/10 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

公开(公告)号：US20240071947A1

公开(公告)日：2024-02-29

申请号：US17823157

申请日：2022-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ling Tsai ,  Lai Wei Chih ,  Meng-Tsan Lee ,  Hung-Pin Chang ,  Li-Han Hsu ,  Chien-Chia Chiu ,  Cheng-Hung Lin

IPC: H01L23/00 ,  H01L23/053 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L23/053 ,  H01L25/18 ,  H01L24/24 ,  H01L24/97 ,  H01L2224/24225 ,  H01L2224/97

Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.

公开(公告)号：US11195802B2

公开(公告)日：2021-12-07

申请号：US16893440

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC: H01L23/552 ,  H01L21/76 ,  H01L23/538 ,  H01L23/00 ,  H01L23/488 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US20210305122A1

公开(公告)日：2021-09-30

申请号：US16835322

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/52

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

公开(公告)号：US20210098391A1

公开(公告)日：2021-04-01

申请号：US16893440

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Cheng Wu ,  Chien-Chia Chiu ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Meng-Tsan Lee ,  Tsung-Shu Lin

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/488 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

公开(公告)号：US11515229B2

公开(公告)日：2022-11-29

申请号：US16835322

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC: H01L23/367 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L21/52 ,  H01L25/00

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

公开(公告)号：US10971425B2

公开(公告)日：2021-04-06

申请号：US16373643

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chia Chiu ,  Li-Han Hsu

IPC: H01L23/40 ,  H01L23/31 ,  H01L23/04 ,  H01L23/16 ,  H01L23/10

Abstract: A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

公开(公告)号：US09941216B2

公开(公告)日：2018-04-10

申请号：US15281043

申请日：2016-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yen Chiu ,  Ching-Fu Chang ,  Chien-Chia Chiu ,  Hsin-Chieh Huang ,  Tsung-Shu Lin ,  Pei-Ti Yu

IPC: H01L23/538 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.

公开(公告)号：US20170345762A1

公开(公告)日：2017-11-30

申请号：US15281043

申请日：2016-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yen Chiu ,  Ching-Fu Chang ,  Chien-Chia Chiu ,  Hsin-Chieh Huang ,  Tsung-Shu Lin ,  Pei-Ti Yu

IPC: H01L23/538 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped portion through the connection portion, and a width of the connection portion decreases along an extending direction from the teardrop shaped portion to the routing line. Furthermore, an integrated fan-out package including the above-mentioned conductive pattern is also provided.