公开(公告)号：US12191287B2

公开(公告)日：2025-01-07

申请号：US18474168

申请日：2023-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L25/10 ,  H01L21/02 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/11 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/427 ,  H01L23/538

Abstract: A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.

公开(公告)号：US12170242B2

公开(公告)日：2024-12-17

申请号：US18064624

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L25/03

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

公开(公告)号：US20240096816A1

公开(公告)日：2024-03-21

申请号：US18521711

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/544 ,  H01L23/3135 ,  H01L24/19

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

公开(公告)号：US11854990B2

公开(公告)日：2023-12-26

申请号：US17176299

申请日：2021-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/97 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/07 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2224/73203 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US20220367212A1

公开(公告)日：2022-11-17

申请号：US17815410

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L25/11 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/42 ,  H01L23/373 ,  H01L21/683

Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

公开(公告)号：US11387217B2

公开(公告)日：2022-07-12

申请号：US17099365

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/552 ,  H01L21/3205 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

公开(公告)号：US11355406B2

公开(公告)日：2022-06-07

申请号：US16895415

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Lin Huang ,  Jung-Hua Chang ,  Jy-Jie Gau ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065

Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.

公开(公告)号：US20210351173A1

公开(公告)日：2021-11-11

申请号：US17382565

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Hsien-Wen Liu ,  Min-Chen Lin

IPC: H01L25/00 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/525 ,  H01L23/532 ,  H01L23/538 ,  H01L21/56 ,  H01L25/065

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

公开(公告)号：US11158588B2

公开(公告)日：2021-10-26

申请号：US16901516

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L33/00 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/538 ,  H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.

公开(公告)号：US11056436B2

公开(公告)日：2021-07-06

申请号：US15175696

申请日：2016-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.