公开(公告)号：US12057507B2

公开(公告)日：2024-08-06

申请号：US18316541

申请日：2023-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming a SiGe layer over a substrate. A silicon layer is formed over the SiGe layer. The silicon layer and the SiGe layer are patterned to form a fin structure over the substrate. The fin structure includes a remaining portion of the SiGe layer and a remaining portion of the silicon layer over the remaining portion of the SiGe layer. A semiconductive capping layer is formed to cover the fin structure. A top portion of the semiconductive capping layer and the remaining portion of the silicon layer are oxidized to form an oxide layer covering the fin structure.

公开(公告)号：US11942476B2

公开(公告)日：2024-03-26

申请号：US17866365

申请日：2022-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/32139 ,  H01L29/165 ,  H01L29/205

Abstract: A method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.

公开(公告)号：US11901190B2

公开(公告)日：2024-02-13

申请号：US15967100

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yuan Tseng ,  Yu-Tien Shen ,  Wei-Liang Lin ,  Chih-Ming Lai ,  Kuo-Cheng Ching ,  Shi Ning Ju ,  Li-Te Lin ,  Ru-Gun Liu

IPC: H01L21/311 ,  H01L21/32 ,  H01L23/528 ,  H01L21/3213

CPC classification number: H01L21/31105 ,  H01L21/32 ,  H01L21/32139 ,  H01L23/528

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

公开(公告)号：US11855084B2

公开(公告)日：2023-12-26

申请号：US17856471

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

公开(公告)号：US20230369458A1

公开(公告)日：2023-11-16

申请号：US18355253

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/6656 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.

公开(公告)号：US11742415B2

公开(公告)日：2023-08-29

申请号：US17178006

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308

CPC classification number: H01L29/6681 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/785

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

公开(公告)号：US11621323B2

公开(公告)日：2023-04-04

申请号：US17135623

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device includes a substrate, an isolation feature over the substrate, a first device fin protruding from the substrate and through the isolation feature, and a second device fin protruding from the substrate and through the isolation feature. The semiconductor device also includes a dielectric fin disposed between the first and second device fins and a metal gate stack engaging the first and second device fins. The dielectric fin separates the metal gate stack into first and second segments and provides electrical isolation between the first and second segments. A portion of the isolation feature is directly under a bottom surface of the dielectric fin.

公开(公告)号：US11515423B2

公开(公告)日：2022-11-29

申请号：US16880864

申请日：2020-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao Kuo ,  Jung-Hao Chang ,  Chao-Hsien Huang ,  Li-Te Lin ,  Kuo-Cheng Ching

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02

Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.

公开(公告)号：US11349016B2

公开(公告)日：2022-05-31

申请号：US16910450

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

Abstract: A fin field effect transistor device structure includes a first fin structure formed over a substrate. The structure also includes a fin top layer formed over a top portion of the first fin structure. The structure also includes a first oxide layer formed across the first fin structure and the fin top layer. The structure also includes a first gate structure formed over the first oxide layer across the first fin structure.

公开(公告)号：US11004960B2

公开(公告)日：2021-05-11

申请号：US16713199

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a second dielectric fin, a semiconductor fin, an epitaxy structure, and a metal gate structure. The first dielectric fin and the second dielectric fin disposed over the substrate. The semiconductor fin is disposed over the substrate, in which the semiconductor fin is between the first dielectric fin and the second dielectric fin. The epitaxy structure covers at least two surfaces of the semiconductor fin, in which the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin. The metal gate structure crosses the first dielectric fin, the second dielectric fin, and the semiconductor fin.