Semiconductor integrated circuit device including means for reducing the
amount of potential variation on a reference voltage line
    2.
    发明授权
    Semiconductor integrated circuit device including means for reducing the amount of potential variation on a reference voltage line 失效
    半导体集成电路器件包括用于减小参考电压线上的电位变化量的装置

    公开(公告)号:US4477736A

    公开(公告)日:1984-10-16

    申请号:US315056

    申请日:1981-10-26

    申请人: Yoshiaki Onishi

    发明人: Yoshiaki Onishi

    摘要: In an MOS memory, a reference voltage is generated to determine an input threshold voltage of the input circuit. Noise fed from various signal wirings to the reference voltage wiring via stray capacitances is reduced by a decoupling capacitance formed between the reference voltage wiring and the ground wiring. The decoupling capacitance, however, permits relatively large levels of noise induced on the ground wiring by changes in the operation current of the circuit to be transmitted to the reference voltage wiring. According to this invention, a capacitance which forms a pair with the decoupling capacitance is provided between the power-supply wiring and the reference voltage wiring. Noise induced on the power-supply wiring by a change in the operation current of the circuit is substantially opposite in polarity to the noise induced on the ground wiring. Therefore, the noise fed from the ground wiring to the reference voltage wiring is cancelled by the capacitance provided between the power-supply wiring and the reference voltage wiring.

    摘要翻译: 在MOS存储器中,产生参考电压以确定输入电路的输入阈值电压。 通过杂散电容从各种信号布线馈送到参考电压布线的噪声通过在参考电压布线和接地布线之间形成的去耦电容而减小。 然而,去耦电容通过改变要传输到参考电压布线的电路的工作电流来允许在接地布线上产生的相当大的噪声水平。 根据本发明,在电源布线和参考电压布线之间设置与去耦电容成对的电容。 通过电路的工作电流的变化对电源布线产生的噪声与接地布线引起的噪声的极性基本相反。 因此,通过电源配线与基准电压配线之间的静电电容来消除从接地线馈送到基准电压配线的噪声。

    Dummy cell structure for MIS dynamic memories
    4.
    发明授权
    Dummy cell structure for MIS dynamic memories 失效
    MIS动态存储器的虚拟单元结构

    公开(公告)号:US4264965A

    公开(公告)日:1981-04-28

    申请号:US83660

    申请日:1979-10-11

    申请人: Yoshiaki Onishi

    发明人: Yoshiaki Onishi

    摘要: A structure of a dummy cell of a one-transistor cell type dynamic RAM made up of MISFETs formed in the shape of an integrated circuit within a single semiconductor substrate, the dummy cell structure comprising a pair of first gate electrode layers which is made of a first polycrystalline silicon layer, a second gate electrode layer which is made of a second polycrystalline silicon layer formed on the semiconductor substrate between the pair of first gate electrode layers through a gate insulating film, means for applying a fixed bias voltage to the second gate electrode layer in order to operate it as a capacitor, means for applying a clear control signal to one of the pair of first gate electrode layers in order to operate it as a clearing MISFET, and means for applying a word select signal to the other first gate electrode layer in order to operate it as a transfer MISFET.

    摘要翻译: 由在单个半导体衬底内形成为集成电路形状的MISFET构成的单晶体管单元型动态RAM的虚设单元的结构,所述虚设单元结构包括一对第一栅极电极层, 第一多晶硅层,通过栅极绝缘膜形成在所述一对第一栅极电极层之间的半导体衬底上的由第二多晶硅层制成的第二栅极电极层,用于向所述第二栅电极施加固定偏置电压的装置 层,以便将其作为电容器操作,用于将清除控制信号施加到该对第一栅电极层之一以便将其作为清除MISFET进行操作的装置,以及用于将字选择信号施加到另一第一栅极的装置 电极层,以便将其作为传输MISFET来操作。