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公开(公告)号：US20130248995A1
公开(公告)日：2013-09-26
申请号：US13607533
申请日：2012-09-07
IPC分类号： H01L29/78 , H01L21/82 , H01L27/088
CPC分类号： H01L29/7827 , H01L21/82 , H01L27/088 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/41775 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type placed above the first semiconductor layer, a second semiconductor layer of the first conductivity type placed above the base layer, multiple gate electrodes having upper end is positioned above the upper surface of the base layer, a lower end positioned below the bottom of the base layer, and contacting the first semiconductor layer, the second semiconductor layer, and the base layer through a gate insulating film, insulating component arranged above the gate electrode in which the upper surface is positioned below the upper surface of the second semiconductor layer, and a conductive layer covering the second semiconductor layer from the upper end to the bottom end.
摘要翻译： 半导体器件包括第一导电类型的第一半导体层，位于第一半导体层上方的第二导电类型的基极层，位于基极层之上的第一导电类型的第二半导体层，具有上端的多个栅电极 位于所述基底层的上表面的上方，位于所述基底层的底部下方的下端，并且通过栅极绝缘膜与所述第一半导体层，所述第二半导体层和所述基底层接触， 栅电极，其上表面位于第二半导体层的上表面下方，以及导电层，其从上端到底端覆盖第二半导体层。
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公开(公告)号：US08502305B2
公开(公告)日：2013-08-06
申请号：US13421816
申请日：2012-03-15
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/2255 , H01L21/26586 , H01L29/0696 , H01L29/0856 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/861
摘要： According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.
摘要翻译： 根据实施例，半导体器件包括第一导电类型的半导体层，设置在半导体层上的第二导电类型的基极区域和设置在基极区域上的第二导电类型的第一接触区域。 该器件包括设置在穿过第一接触区域和基极区域的沟槽中的栅电极，以及设置在栅极上并包含第一导电型杂质元素的层间绝缘膜。 该器件还包括设置在层间绝缘膜和第一接触区域之间的第一导电类型的源极区域，源极区域与层间绝缘膜的侧面接触并且在基极区域中延伸。
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3.发明授权Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 有权包括用作高速开关装置的场效应晶体管和功率器件的半导体装置公开(公告)号：US08502309B2
公开(公告)日：2013-08-06
申请号：US12645072
申请日：2009-12-22
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。
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公开(公告)号：US08253398B2
公开(公告)日：2012-08-28
申请号：US12500015
申请日：2009-07-09
申请人： Kazutoshi Nakamura , Norio Yasuhara
发明人： Kazutoshi Nakamura , Norio Yasuhara
CPC分类号： H02M3/1588 , H02M1/32 , H02M3/158 , Y02B70/1466
摘要： A semiconductor device includes: a high-side switching element having a first switching element connected between an input voltage line and an inductive load; and a low-side switching element having a second switching element and a third switching element that are connected in parallel between the inductive load and a reference voltage line. A surge current is discharged through the third switching element to the reference voltage line when a surge is applied to a terminal connected to the inductive load in the low-side switching element.
摘要翻译： 一种半导体器件包括：高侧开关元件，其具有连接在输入电压线和感性负载之间的第一开关元件; 以及具有第二开关元件和第三开关元件的低侧开关元件，其并联连接在感性负载和参考电压线之间。 当浪涌被施加到连接到低侧开关元件中的感性负载的端子时，浪涌电流通过第三开关元件放电到参考电压线。
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5.发明授权公开(公告)号：US07998849B2
公开(公告)日：2011-08-16
申请号：US12716352
申请日：2010-03-03
IPC分类号： H01L21/336
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。
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6.发明授权Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 失效包括用作高速开关装置的场效应晶体管和功率器件的半导体装置公开(公告)号：US07646059B2
公开(公告)日：2010-01-12
申请号：US11501715
申请日：2006-08-10
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。
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7.发明授权Semiconductor device including power MOS field-effect transistor and driver circuit driving thereof 失效包括功率MOS场效应晶体管和其驱动电路驱动的半导体器件公开(公告)号：US07579669B2
公开(公告)日：2009-08-25
申请号：US11549297
申请日：2006-10-16
IPC分类号： H01L27/00
CPC分类号： H02M3/158 , H01L27/0922 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/7813 , H01L29/7835 , H01L2924/0002 , H02M1/08 , H02M7/003 , H01L2924/00
摘要： A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.
摘要翻译： 半导体器件包括高侧开关元件，驱动电路和低侧开关元件。 高侧开关元件形成在第一半导体基板上，其一端具有输入电压的电流通路，电流路径的另一端与电感连接。 驱动电路形成在形成有高侧开关元件的第一半导体基板上，驱动高侧开关元件。 低侧开关元件形成在与第一半导体衬底分离的第二半导体衬底上，并且具有连接到电感的漏极和被提供参考电位的源极。
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8.发明申请公开(公告)号：US20070040216A1
公开(公告)日：2007-02-22
申请号：US11505337
申请日：2006-08-17
IPC分类号： H01L29/76
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。
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9.发明授权公开(公告)号：US07138698B2
公开(公告)日：2006-11-21
申请号：US11007254
申请日：2004-12-09
IPC分类号： H01L23/58
CPC分类号： H02M3/158 , H01L27/0922 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/7813 , H01L29/7835 , H01L2924/0002 , H02M1/08 , H02M7/003 , H01L2924/00
摘要： A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.
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公开(公告)号：US06720618B2
公开(公告)日：2004-04-13
申请号：US10055947
申请日：2002-01-28
IPC分类号： H01L2976
CPC分类号： H01L21/26513 , H01L29/04 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/41 , H01L29/4175 , H01L29/42372 , H01L29/42376 , H01L29/66659 , H01L29/66712 , H01L29/7802 , H01L29/7835
摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.
摘要翻译： 一种功率MOSFET器件，包括第一导电类型的低电阻衬底，形成在低电阻衬底上的第一导电类型的高电阻外延层，形成在高电阻外延表面区域中的第二导电类型的基极层 形成在基底层的表面区域中的第一导电类型的源极区域，形成在基极层的表面上以与源极区域接触的栅极绝缘膜，形成在栅极绝缘膜上的栅电极， 以及形成在所述高电阻外延层的与所述源极区域和所述栅极电极相反的表面上的所述第一导电类型的LDD层，其中所述LDD层和所述低电阻衬底通过所述高电阻外延层彼此连接 。
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