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    METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF POWER PATH PROTECTION DEVICES
    2.
    发明申请
    METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF POWER PATH PROTECTION DEVICES 有权

    公开(公告)号：US20210066909A1

    公开(公告)日：2021-03-04

    申请号：US17011522

    申请日：2020-09-03

    Applicant: Texas Instruments Incorporated

    Inventor： Yogesh Kumar Ramadass ,  Ujwal Radhakrishna ,  Jeffrey Morroni

    IPC: H02H7/20 ,  H01L23/525 ,  H03K17/687

    Abstract: An example integrated circuit includes: a substrate and a first metal fuse layer on the substrate, the first metal fuse layer having first and second electrical contacts, the first electrical contact adapted to be coupled to an input terminal, the second electrical contact adapted to be coupled to a diode. The example integrated circuit further includes a second metal fuse layer on the substrate, the second metal fuse layer having third and fourth electrical contacts, the third electrical contact coupled to the second electrical contact and adapted to be coupled to the diode, the fourth electrical contact coupled to a shunt circuit.

    INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE
    4.
    发明申请
    INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE 有权

    公开(公告)号：US20240405024A1

    公开(公告)日：2024-12-05

    申请号：US18534056

    申请日：2023-12-08

    Applicant: Texas Instruments Incorporated

    Inventor： Ujwal Radhakrishna ,  Yoganand Saripalli ,  Zhikai Tang ,  Timothy Merkin ,  Jungwoo Joh

    IPC: H01L27/095 ,  H01L27/02 ,  H01L29/20 ,  H01L29/778

    Abstract: The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

    SELF-ALIGNED GATE STRUCTURE
    6.
    发明申请
    SELF-ALIGNED GATE STRUCTURE 有权

    公开(公告)号：US20250142866A1

    公开(公告)日：2025-05-01

    申请号：US18783955

    申请日：2024-07-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Zhikai Tang ,  Masahiko Higashi ,  Ujwal Radhakrishna ,  Jungwoo Joh

    IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

    Abstract: The present disclosure generally relates to semiconductor processing for a self-aligned gate structure and corresponding semiconductor device. In an example, a semiconductor device includes a semiconductor substrate, a semiconductor gate layer, an offset dielectric layer, and a gate metal contact. The semiconductor gate layer is over the semiconductor substrate. The offset dielectric layer is over the semiconductor gate layer. The gate metal contact is over the offset dielectric layer and is through an opening through the offset dielectric layer. The gate metal contact contacts the semiconductor gate layer through the opening through the offset dielectric layer. A first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned over the semiconductor substrate.

    SEMICONDUCTOR DEVICE WITH GATE ELECTRICAL CONTACT FORMING JUNCTIONS HAVING DIFFERENT ENERGY BARRIER HEIGHTS TO GATE LAYER
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH GATE ELECTRICAL CONTACT FORMING JUNCTIONS HAVING DIFFERENT ENERGY BARRIER HEIGHTS TO GATE LAYER 有权

    公开(公告)号：US20250048667A1

    公开(公告)日：2025-02-06

    申请号：US18361997

    申请日：2023-07-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ujwal Radhakrishna ,  Zhikai Tang ,  Johan Strydom ,  Jungwoo Joh

    IPC: H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872

    Abstract: The present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. In an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain and source electrical contacts are on the semiconductor substrate. The barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. The gate layer is over the barrier layer. The gate layer includes first and second semiconductor portions. The gate electrical contact contacts the gate layer. The gate electrical contact includes first and second metal portions. The first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. The first and second junctions have different energy barrier heights.

    GROUP III-N DEVICE INCLUDING SOURCE CONTACT CONNECTED TO SUBSTRATE THROUGH TRENCH
    10.
    发明申请
    GROUP III-N DEVICE INCLUDING SOURCE CONTACT CONNECTED TO SUBSTRATE THROUGH TRENCH 有权

    公开(公告)号：US20250098266A1

    公开(公告)日：2025-03-20

    申请号：US18756202

    申请日：2024-06-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Zhikai Tang ,  Jungwoo Joh ,  Ujwal Radhakrishna

    IPC: H01L29/417 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

    Abstract: Semiconductor devices with a source contact extending into a substrate are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate stack is disposed over the barrier layer in the gate region. A source contact in the source region extends into the semiconductor substrate, including a first contact with a 2DEG in the heterojunction structure and a second contact with the semiconductor substrate.

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