公开(公告)号：US5269005A

公开(公告)日：1993-12-07

申请号：US761185

申请日：1991-09-17

申请人： Thomas F. Heil ,  Edward A. McDonald ,  Gene F. Young

发明人： Thomas F. Heil ,  Edward A. McDonald ,  Gene F. Young

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit. In response to the retry signal, the processor is taken off the system bus and not allowed to regain the system bus until the buffered data is written to main memory. A bus busy signal is raised and will not be lowered until the data is written to main memory. When the busy signal is lowered, the processor regains the system bus and receives an interrupt vector from the interrupt controller. I/O bus ownership is locked until the interrupted processor has received an interrupt vector and the IAK cycle is complete. If no buffered data remains in the interface circuit, no retry signal is generated. The interrupt controller waits a predefined period of time for a retry signal and if none is detected, the interrupt controller issues an appropriate interrupt vector to complete the IAK cycle. For multiple I/O buses, preferably only one interface circuit retries processors issuing IAK cycles.

摘要翻译： 在处理系统中，对中断确认周期的任何响应都被推迟，直到将从子系统I / O总线上的代理写入缓冲数据传送到系统的主存储器得到保证。 为了加快系统运行，由I / O总线上的代理程序写入主存的数据被缓存在接口电路中。 一旦数据被缓冲，I / O总线代理被释放并中断系统总线上的处理器，指示完成数据写入。 使用紧密耦合的中断控制器，以便代理不需要拥有I / O或系统总线来产生中断。 中断的处理器在系统总线上发出中断确认（IAK）周期，以从中断控制器接收中断向量。 接口电路识别IAK周期，并且如果缓冲数据保留在接口电路中，则为处理器生成重试信号。 响应于重试信号，处理器从系统总线中取出，不允许重新获得系统总线，直到缓冲的数据被写入主存储器。 总线忙信号升高，直到数据写入主存储器才会降低。 当忙信号降低时，处理器恢复系统总线并从中断控制器接收中断向量。 I / O总线所有权被锁定，直到中断处理器收到中断向量并且IAK周期完成。 如果接口电路中没有缓冲的数据，则不会产生重试信号。 中断控制器等待重试信号的预定义时间段，如果没有检测到，中断控制器发出适当的中断向量来完成IAK周期。 对于多个I / O总线，最好只有一个接口电路重试发出IAK周期的处理器。

公开(公告)号：US5418914A

公开(公告)日：1995-05-23

申请号：US143393

申请日：1993-10-25

申请人： Thomas F. Heil ,  Edward A. McDonald ,  Gene F. Young ,  Craig A. Walrath ,  James M. Ottinger ,  Marti D. Miller

发明人： Thomas F. Heil ,  Edward A. McDonald ,  Gene F. Young ,  Craig A. Walrath ,  James M. Ottinger ,  Marti D. Miller

IPC分类号： G06F13/36 ,  G06F13/362

CPC分类号： G06F13/362

摘要： A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource. Upon negation of the busy signal, all bus masters will be permitted to compete for ownership of the bus.

摘要翻译： 一种用于优化在计算机系统中使用第一总线的重试方案，该计算机系统包括通过第一总线连接到接口电路和第二总线的多个总线主机。 接口电路包括当第二总线处于忙状态时产生忙信号的逻辑和当第二总线处于忙状态时当总线主机寻址接口电路时产生重试信号的逻辑。 每个总线主机包括用于在从接口电路接收到重试信号时接收重试信号和放弃公共总线的控制的逻辑。 总线仲裁器包括用于接收忙信号的逻辑，并且阻止任何总线主机寻求访问第二总线参与用于控制公共第一总线的仲裁，直到忙信号被否定为止。 因此，在忙信号期间，第一总线可以由不需要访问共享资源的任何总线主控器来控制。 在否定忙碌信号后，所有巴士主人将被允许竞争总线的所有权。

公开(公告)号：US5359715A

公开(公告)日：1994-10-25

申请号：US760786

申请日：1991-09-16

申请人： Thomas F. Heil ,  Craig A. Walrath ,  Jimmy D. Pike ,  Edward A. McDonald ,  Arthur F. Cochcroft, Jr. ,  P. Chris Raeuber ,  Daniel C. Robbins ,  Gene F. Young

发明人： Thomas F. Heil ,  Craig A. Walrath ,  Jimmy D. Pike ,  Edward A. McDonald ,  Arthur F. Cochcroft, Jr. ,  P. Chris Raeuber ,  Daniel C. Robbins ,  Gene F. Young

IPC分类号： G06F15/16 ,  G06F13/24 ,  G06F13/36 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F13/24

摘要： Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

摘要翻译： 多处理器系统被配置为包括至少两个系统或存储器总线，其中至少两个处理器耦合到每个系统总线，以及耦合到系统总线的至少两个I / O总线，以提供多个扩展槽， 为每个I / O总线以单个系统总线负载为代价的系统的相应数量的I / O总线代理。 系统和I / O总线中的每一个被独立地仲裁以定义用于本发明的多个处理器系统的解耦总线系统。 用于系统的主存储器由至少两个存储器交错组成，每个存储器交错可以通过系统总线同时访问。 每个I / O总线通过I / O接口电路连接到系统总线，I / O接口电路缓冲写入主存储器的数据或由I / O总线代理器读取存储器交错的数据。

公开(公告)号：US06098113A

公开(公告)日：2000-08-01

申请号：US417701

申请日：1995-04-06

申请人： Thomas F. Heil ,  Edward A. McDonald ,  James M. Ottinger ,  Jeffrey A. Hawkey

发明人： Thomas F. Heil ,  Edward A. McDonald ,  James M. Ottinger ,  Jeffrey A. Hawkey

IPC分类号： G06F13/42 ,  G06F3/00

CPC分类号： G06F13/423

摘要： Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.

摘要翻译： 多个子系统I / O（输入/输出）总线通过接口电路耦合到计算机系统的一个或多个系统总线，所述接口电路执行存储器空间的必要解码以及用于分配存储器部分的I / O（输入/输出） 空间和每个I / O（输入/输出）总线的I / O（输入/输出）空间。 接口电路还可以转换每个I / O（输入/输出）总线中的固定地址，以允许计算机系统正确操作I / O（输入/输出）总线。 接口电路由计算机系统编程，以便为相应的I / O（输入/输出）总线定义分配的存储空间和I / O（输入/输出）空间。 通过将合适的值写入并入每个接口电路的配置寄存器中，在系统配置时执行I / O（输入/输出）总线的编程。

公开(公告)号：US5327540A

公开(公告)日：1994-07-05

申请号：US16652

申请日：1993-02-01

申请人： Thomas F. Heil ,  Daniel C. Robbins ,  Edward A. McDonald

发明人： Thomas F. Heil ,  Daniel C. Robbins ,  Edward A. McDonald

IPC分类号： G06F13/362

CPC分类号： G06F13/362

摘要： A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.

摘要翻译： 一种用于在计算机系统内优化配置数据缓冲器的缓冲器管理方案，其包括通过微通道总线连接的多个总线主机和数据缓冲器到诸如存储器之类的共享资源。 该方案解码分配给总线主机的唯一的四位微通道仲裁值，以检索存储在每个总线主机的不同配置参数的寄存器文件中的缓冲区配置参数。 根据从寄存器文件检索的参数数据，数据缓冲区被动态地配置为具有最佳性能，每个总线主机具有对微通道总线的控制。

公开(公告)号：US6026472A

公开(公告)日：2000-02-15

申请号：US881413

申请日：1997-06-24

申请人： Larry C. James ,  Arthur F. Cochcroft, Jr. ,  Peter Washington ,  Edward A. McDonald

发明人： Larry C. James ,  Arthur F. Cochcroft, Jr. ,  Peter Washington ,  Edward A. McDonald

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0813 ,  G06F2212/2542

摘要： A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.

摘要翻译： 为了优化包括分布式系统存储器在内的多节点NUMA架构计算机系统中的存储器和处理分配的目的，同时获得用于系统存储器（页）的大量连续部分的存储器访问位置信息的硬件方法。 页面访问监视逻辑包含在包含共享系统存储器的一部分的每个处理节点内。 该页面访问监视逻辑维护多个页面访问计数器，每个页面访问计数器对应于共享系统存储器内的不同存储器页面地址。 每当处理节点产生需要访问系统存储器内的存储器地址的事务时，页面访问监视逻辑增加与寻求访问的存储器地址相对应的页面访问计数器中的计数值。 因此，创建了可用于优化计算机系统中的存储器和处理分配的存储器访问模式的记录。

公开(公告)号：US6120535A

公开(公告)日：2000-09-19

申请号：US975584

申请日：1997-11-21

申请人： Edward A. McDonald ,  Michael Henson ,  Joe W. Young

发明人： Edward A. McDonald ,  Michael Henson ,  Joe W. Young

IPC分类号： A61F2/00 ,  A61F2/82 ,  A61F2/92 ,  A61N5/10

CPC分类号： A61F2/962 ,  A61F2/92 ,  A61F2/0077 ,  A61F2002/826 ,  A61F2002/8483 ,  A61F2002/9517 ,  A61F2210/0076 ,  A61F2210/0095 ,  A61F2220/005 ,  A61F2220/0075 ,  A61F2250/0067 ,  A61N5/1002

摘要： Disclosed is a tubular microporous prosthesis formed by rolling a flexible sheet around a longitudinal axis. Preferably, the prosthesis is self expandable under the radially outwardly directed spring bias of the rolled sheet. At least a portion of the sheet may be provided with a coating to affect the physical and/or biological properties of the prosthesis.

摘要翻译： 公开了一种通过围绕纵向轴线滚动柔性片而形成的管状微孔假体。 优选地，假体在轧制板的径向向外指向的弹簧偏压下是可自膨的。 片材的至少一部分可以设置有涂层以影响假体的物理和/或生物学性质。

公开(公告)号：US6047316A

公开(公告)日：2000-04-04

申请号：US989617

申请日：1997-12-12

申请人： Richard R. Barton ,  Arthur F. Cochcroft, Jr. ,  Edward A. McDonald ,  Robert J. Miller ,  Byron L. Reams ,  Roy M. Stevens ,  Billy K. Taylor

发明人： Richard R. Barton ,  Arthur F. Cochcroft, Jr. ,  Edward A. McDonald ,  Robert J. Miller ,  Byron L. Reams ,  Roy M. Stevens ,  Billy K. Taylor

IPC分类号： G06F9/46 ,  G06F12/00

CPC分类号： G06F9/52 ,  G06F12/0817

摘要： A multiprocessor computing apparatus that includes a mechanism for favoring at least one processor over another processor to achieve more equitable access to cached data. Logic for detecting when, for example, a remote and a local processor are attempting to access data from the cache of another local processor is disclosed. Logic that provides an advantage to the remote processor in a manner that achieves fairer access among the various processors is also disclosed.

摘要翻译： 一种多处理器计算装置，其包括用于在另一处理器上有利于至少一个处理器以实现对缓存数据的更公平访问的机制。 公开了用于检测例如远程和本地处理器何时尝试从另一本地处理器的高速缓存访​​问数据的逻辑。 还公开了以在各种处理器之间实现更公平的访问的方式为远程处理器提供优势的逻辑。

公开(公告)号：US06292860B1

公开(公告)日：2001-09-18

申请号：US08991697

申请日：1997-12-16

申请人： Arthur F. Cochcroft, Jr. ,  Edward A. McDonald ,  Byron L. Reams ,  Harry W. Scrivener ,  Bobby W. Batchler

发明人： Arthur F. Cochcroft, Jr. ,  Edward A. McDonald ,  Byron L. Reams ,  Harry W. Scrivener ,  Bobby W. Batchler

IPC分类号： G06F1300

CPC分类号： G06F9/524 ,  G06F13/36 ,  G06F13/4036

摘要： A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.

摘要翻译： 计算机的死锁避免系统。 在多总线多处理器计算机中，一个处理器可以请求总线上的锁定，以执行锁定的周期，从而阻止所有其他处理器和其他代理人访问总线。 此外，冲突代理实际上可以锁定处理器所需的资源来完成请求锁的周期。 这两个锁可能会造成死锁的情况，使计算机停顿：处理器和冲突代理程序都锁定了另一个所需的资源。 根据本发明，当处理器请求锁定的周期时，所有其他操作都被挂起在计算机中。 然后排在内存控制器中的队列被清空。 如果代理所请求的进程占用所请求的锁定周期所需的资源（例如网桥），该资源将被释放。 然后执行锁定循环。

公开(公告)号：US6058475A

公开(公告)日：2000-05-02

申请号：US935910

申请日：1997-09-22

申请人： Edward A. McDonald ,  Bobby W. Batchler

发明人： Edward A. McDonald ,  Bobby W. Batchler

IPC分类号： G06F11/00 ,  G06F15/177

CPC分类号： G06F11/1417 ,  G06F15/177

摘要： A system for booting a multi-processor computer. If a normal boot attempt fails, different processors are selected, one-at-a-time, for performing the boot routine. During the boot routing, all other processors are held inactive. After boot, processors are tested for health. Non-healthy processors are held inactive, and healthy processors are activated as usual.

摘要翻译： 用于启动多处理器计算机的系统。 如果正常启动尝试失败，则会一次一个地选择不同的处理器来执行引导例程。 在引导路由期间，所有其他处理器保持不活动。 引导后，处理器进行健康测试。 非健康的处理器保持不活动状态，健康的处理器照常激活。