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22 条记录 (耗时 0.034 秒)

    Method for preventing deadlock by suspending operation of processors, bridges, and devices
    2.
    发明授权
    Method for preventing deadlock by suspending operation of processors, bridges, and devices 失效
    通过暂停处理器，网桥和设备的操作来防止死锁的方法

    公开(公告)号：US06292860B1

    公开(公告)日：2001-09-18

    申请号：US08991697

    申请日：1997-12-16

    申请人： Arthur F. Cochcroft, Jr. ,  Edward A. McDonald ,  Byron L. Reams ,  Harry W. Scrivener ,  Bobby W. Batchler

    发明人： Arthur F. Cochcroft, Jr. ,  Edward A. McDonald ,  Byron L. Reams ,  Harry W. Scrivener ,  Bobby W. Batchler

    IPC分类号： G06F1300

    CPC分类号： G06F9/524 ,  G06F13/36 ,  G06F13/4036

    摘要： A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.

    摘要翻译： 计算机的死锁避免系统。 在多总线多处理器计算机中，一个处理器可以请求总线上的锁定，以执行锁定的周期，从而阻止所有其他处理器和其他代理人访问总线。 此外，冲突代理实际上可以锁定处理器所需的资源来完成请求锁的周期。 这两个锁可能会造成死锁的情况，使计算机停顿：处理器和冲突代理程序都锁定了另一个所需的资源。 根据本发明，当处理器请求锁定的周期时，所有其他操作都被挂起在计算机中。 然后排在内存控制器中的队列被清空。 如果代理所请求的进程占用所请求的锁定周期所需的资源（例如网桥），该资源将被释放。 然后执行锁定循环。

    Method and apparatus for determining memory page access information in a non-uniform memory access computer system
    3.
    发明授权
    Method and apparatus for determining memory page access information in a non-uniform memory access computer system 失效
    用于在不均匀的存储器访问计算机系统中确定存储器页面访问信息的方法和装置

    公开(公告)号：US6026472A

    公开(公告)日：2000-02-15

    申请号：US881413

    申请日：1997-06-24

    申请人： Larry C. James ,  Arthur F. Cochcroft, Jr. ,  Peter Washington ,  Edward A. McDonald

    发明人： Larry C. James ,  Arthur F. Cochcroft, Jr. ,  Peter Washington ,  Edward A. McDonald

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0813 ,  G06F2212/2542

    摘要： A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.

    摘要翻译： 为了优化包括分布式系统存储器在内的多节点NUMA架构计算机系统中的存储器和处理分配的目的，同时获得用于系统存储器（页）的大量连续部分的存储器访问位置信息的硬件方法。 页面访问监视逻辑包含在包含共享系统存储器的一部分的每个处理节点内。 该页面访问监视逻辑维护多个页面访问计数器，每个页面访问计数器对应于共享系统存储器内的不同存储器页面地址。 每当处理节点产生需要访问系统存储器内的存储器地址的事务时，页面访问监视逻辑增加与寻求访问的存储器地址相对应的页面访问计数器中的计数值。 因此，创建了可用于优化计算机系统中的存储器和处理分配的存储器访问模式的记录。

    System and method of establishing error precedence in a computer system
    5.
    发明授权
    System and method of establishing error precedence in a computer system 失效
    在计算机系统中建立错误优先的系统和方法

    公开(公告)号：US5758065A

    公开(公告)日：1998-05-26

    申请号：US565520

    申请日：1995-11-30

    申请人： Byron L. Reams ,  Edward A. McDonald

    发明人： Byron L. Reams ,  Edward A. McDonald

    IPC分类号： G06F11/07 ,  G06F11/00

    CPC分类号： G06F11/0745 ,  G06F11/0724 ,  G06F11/079

    摘要： A system and method of establishing error precedence in a computer system which determine a first error to occur. The system determines the order of occurrence of errors in a computer system and includes error precedence modules which record and order errors that occur on a first bus with error that occur on a second bus. Diagnostic processing circuitry reads the errors stored within the error precedence modules and their order of occurrence and determines which bus the first error occurred on.

    摘要翻译： 一种在计算机系统中建立错误优先级的系统和方法，其确定发生第一错误。 系统确定计算机系统中错误发生的顺序，并且包括错误优先模块，其记录和排序在第二总线上发生错误的第一总线上发生的错误。 诊断处理电路读取错误优先模块中存储的错误及其出现顺序，并确定发生第一个错误的总线。

    System and method for terminating lock-step sequences in a multiprocessor system
    6.
    发明授权
    System and method for terminating lock-step sequences in a multiprocessor system 失效
    用于在多处理器系统中终止锁步序列的系统和方法

    公开(公告)号：US06754787B2

    公开(公告)日：2004-06-22

    申请号：US10302372

    申请日：2002-11-22

    申请人： Robert J. Miller ,  Edward A. McDonald

    发明人： Robert J. Miller ,  Edward A. McDonald

    IPC分类号： G06F1200

    CPC分类号： G06F11/0793 ,  G06F9/52 ,  G06F11/0724 ,  G06F13/1663

    摘要： There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.

    摘要翻译： 提供了一种用于包含耦合到主存储器的多个处理器的处理系统中的控制电路，用于扰乱从处理器接收到的锁步骤序列的存储器请求。 控制电路包括存储器请求发生器，用于产生至少一个可操作以终止锁定步骤序列的存储器请求的存储器请求。

    System and method for improved transfer of data between multiple processors and I/O bridges
    7.
    发明授权
    System and method for improved transfer of data between multiple processors and I/O bridges 失效
    用于改善多处理器和I / O桥之间的数据传输的系统和方法

    公开(公告)号：US06128677A

    公开(公告)日：2000-10-03

    申请号：US943677

    申请日：1997-10-15

    申请人： Robert J. Miller ,  Edward A. McDonald

    发明人： Robert J. Miller ,  Edward A. McDonald

    IPC分类号： G06F13/40 ,  G06F13/36

    CPC分类号： G06F13/4031

    摘要： A controller is provided, for use in a processing system containing a plurality of processors operable to communicate with a plurality of I/O devices, for directing a first I/O request issued by a first selected one of the plurality of processors to a targeted one of the I/O devices. The controller device comprises a counter for counting a number of retries associated with the first I/O request and comparison circuitry for comparing a count value in the counter with a first predetermined limit, wherein the controller, in response to a determination that the count value in the counter exceeds the first predetermined limit, blocks all other I/O requests issued by the plurality of processors from being directed to the targeted I/O device.

    摘要翻译： 提供控制器，用于包含可操作以与多个I / O设备进行通信的多个处理器的处理系统，用于将由多个处理器中的第一选定的处理器发出的第一I / O请求引导到目标 其中一个I / O设备。 控制器装置包括用于计数与第一I / O请求相关联的重试次数的计数器和用于将计数器中的计数值与第一预定极限进行比较的比较电路，其中控制器响应于确定计数值 在计数器中超过第一预定限制，阻止由多个处理器发出的所有其它I / O请求被引导到目标I / O设备。

    System and method for terminating lock-step sequences in a multiprocessor system
    8.
    发明授权
    System and method for terminating lock-step sequences in a multiprocessor system 失效
    用于在多处理器系统中终止锁步序列的系统和方法

    公开(公告)号：US06560682B1

    公开(公告)日：2003-05-06

    申请号：US08943676

    申请日：1997-10-03

    申请人： Robert J. Miller ,  Edward A. McDonald

    发明人： Robert J. Miller ,  Edward A. McDonald

    IPC分类号： G06F1200

    CPC分类号： G06F11/0793 ,  G06F9/52 ,  G06F11/0724 ,  G06F13/1663

    摘要： There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.

    摘要翻译： 提供了一种用于包含耦合到主存储器的多个处理器的处理系统中的控制电路，用于扰乱从处理器接收到的锁步骤序列的存储器请求。 控制电路包括存储器请求发生器，用于产生至少一个可操作以终止锁定步骤序列的存储器请求的存储器请求。

    Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus
    9.
    发明授权
    Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus 失效
    用于多个输入/输出（I / O）总线到系统总线的地址转换和分配的装置和方法

    公开(公告)号：US06098113A

    公开(公告)日：2000-08-01

    申请号：US417701

    申请日：1995-04-06

    申请人： Thomas F. Heil ,  Edward A. McDonald ,  James M. Ottinger ,  Jeffrey A. Hawkey

    发明人： Thomas F. Heil ,  Edward A. McDonald ,  James M. Ottinger ,  Jeffrey A. Hawkey

    IPC分类号： G06F13/42 ,  G06F3/00

    CPC分类号： G06F13/423

    摘要： Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.

    摘要翻译： 多个子系统I / O（输入/输出）总线通过接口电路耦合到计算机系统的一个或多个系统总线，所述接口电路执行存储器空间的必要解码以及用于分配存储器部分的I / O（输入/输出） 空间和每个I / O（输入/输出）总线的I / O（输入/输出）空间。 接口电路还可以转换每个I / O（输入/输出）总线中的固定地址，以允许计算机系统正确操作I / O（输入/输出）总线。 接口电路由计算机系统编程，以便为相应的I / O（输入/输出）总线定义分配的存储空间和I / O（输入/输出）空间。 通过将合适的值写入并入每个接口电路的配置寄存器中，在系统配置时执行I / O（输入/输出）总线的编程。