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43 条记录 (耗时 0.025 秒)

    Predefined critical spaces in IC patterning to reduce line end pull back
    2.
    发明授权
    Predefined critical spaces in IC patterning to reduce line end pull back 有权
    IC图案化中预定的关键空间，以减少线端拉回

    公开(公告)号：US07071085B1

    公开(公告)日：2006-07-04

    申请号：US10852876

    申请日：2004-05-25

    申请人： Todd P. Lukanc ,  Luigi Capodieci ,  Christopher A. Spence ,  Joerg Reiss ,  Sarah N. McGowan

    发明人： Todd P. Lukanc ,  Luigi Capodieci ,  Christopher A. Spence ,  Joerg Reiss ,  Sarah N. McGowan

    IPC分类号： H01L21/475

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  Y10S438/947

    摘要： The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.

    摘要翻译： 本发明包括一种制造这种设备的装置和方法，包括以下步骤：形成待图案化的层，在待图案化的层上形成感光层，使光敏层形成图案，形成包括水平线和垂直线 将图案转移到待图案化的层上，在图案上形成第二感光层，图案化第二感光层以形成包括在水平线和垂直线之间对准的空间的第二图案，并且转印 第二图案到要被图案化的层以形成包括水平线和在其间具有空间的垂直线的第三图案，该空间包括在光刻的分辨率极限下可实现的宽度尺寸。

    Reduce line end pull back by exposing and etching space after mask one trim and etch
    3.
    发明授权
    Reduce line end pull back by exposing and etching space after mask one trim and etch 有权
    通过在掩模一次修整和蚀刻后曝光和蚀刻空间来减少线端拉回

    公开(公告)号：US07015148B1

    公开(公告)日：2006-03-21

    申请号：US10852883

    申请日：2004-05-25

    申请人： Todd P. Lukanc ,  Luigi Capodieci ,  Christopher A. Spence ,  Joerg Reiss ,  Sarah N. McGowan

    发明人： Todd P. Lukanc ,  Luigi Capodieci ,  Christopher A. Spence ,  Joerg Reiss ,  Sarah N. McGowan

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/0276 ,  H01L21/28123 ,  H01L21/28282 ,  H01L21/32139

    摘要： The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension. The method includes the steps of: forming a photosensitive layer to be patterned, patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween, transferring the pattern to at least one underlying layer using the patterned photosensitive layer, forming a second photosensitive layer over the patterned at least one underlying layer, patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer, and transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension.

    摘要翻译： 本发明是制造半导体器件和这种半导体器件的方法。 半导体器件包括集成电路图案，其包括水平线，垂直线和它们之间的空间，该空间包括精确的宽度尺寸。 该方法包括以下步骤：形成待图案化的感光层，图案化感光层以形成包括主水平线和主垂直线的图案，其间没有间隙，使用图案化将图案转移到至少一个下层 在所述图案化的至少一个下层上形成第二感光层，对所述第二感光层进行图案化，以形成第二图案，所述第二图案包括对准以剖开在所述至少一个下层中形成的水​​平线和垂直线的主空间， 以及将所述第二图案转移到所述至少一个下层，以形成包括水平线和在其间具有空间的垂直线的第三图案，所述空间包括精确的宽度尺寸。

    Microdevice having non-linear structural component and method of fabrication
    4.
    发明授权
    Microdevice having non-linear structural component and method of fabrication 有权
    具有非线性结构部件和制造方法的微器件

    公开(公告)号：US06995433B1

    公开(公告)日：2006-02-07

    申请号：US10791250

    申请日：2004-03-02

    申请人： Todd P. Lukanc ,  Sarah N. McGowan ,  Luigi Capodieci ,  Bhanwar Singh ,  Joerg Reiss

    发明人： Todd P. Lukanc ,  Sarah N. McGowan ,  Luigi Capodieci ,  Bhanwar Singh ,  Joerg Reiss

    IPC分类号： H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/7835 ,  H01L21/32139 ,  H01L29/4238 ,  H01L29/66659

    摘要： A microdevice for forming a part of an integrated circuit and method for fabricating are disclosed. The microdevice can include a first conductive region and a second conductive region having a channel region interposed therebetween. The mircodevice has a channel region controlling component disposed over the channel region and separated therefrom by at least one dielectric layer. The channel region controlling component has a non-linear structural characteristic derived from a non-linear structural characteristic of a photo resist feature used as an etch mask for the channel region controlling component.

    摘要翻译： 公开了一种用于形成集成电路的一部分的微型器件及其制造方法。 微器件可以包括第一导电区域和介于其之间的沟道区域的第二导电区域。 微电极具有设置在沟道区域上并由至少一个电介质层分离的沟道区域控制部件。 通道区域控制部件具有从用作沟道区域控制部件的蚀刻掩模的光致抗蚀剂特征的非线性结构特性导出的非线性结构特性。

    Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results
    7.
    发明授权
    Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results 有权
    计量配方生成方法和系统，设计，模拟和计量结果的审查和分析

    公开(公告)号：US07207017B1

    公开(公告)日：2007-04-17

    申请号：US10865047

    申请日：2004-06-10

    申请人： Cyrus Tabery ,  Chris Haidinyak ,  Todd P. Lukanc ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

    发明人： Cyrus Tabery ,  Chris Haidinyak ,  Todd P. Lukanc ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

    摘要翻译： 生成计量配方的方法包括识别设备布局内的感兴趣区域。 可以提供对应于所识别的感兴趣区域的坐标列表并用于创建剪切布局，其可以由剪切布局数据文件表示。 裁剪的布局数据文件和相应的坐标列表可以被提供并转换成用于在测试处理的晶片和/或掩模版时引导一个或多个计量仪器的计量配方。 根据测量要求收到的实验测量结果可以与相应的设计数据和仿真数据相关联，并存储在可数据库系统中。