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1.发明授权公开(公告)号：US06995433B1
公开(公告)日：2006-02-07
申请号：US10791250
申请日：2004-03-02
IPC分类号： H01L29/94 , H01L31/062
CPC分类号： H01L29/7835 , H01L21/32139 , H01L29/4238 , H01L29/66659
摘要： A microdevice for forming a part of an integrated circuit and method for fabricating are disclosed. The microdevice can include a first conductive region and a second conductive region having a channel region interposed therebetween. The mircodevice has a channel region controlling component disposed over the channel region and separated therefrom by at least one dielectric layer. The channel region controlling component has a non-linear structural characteristic derived from a non-linear structural characteristic of a photo resist feature used as an etch mask for the channel region controlling component.
摘要翻译： 公开了一种用于形成集成电路的一部分的微型器件及其制造方法。 微器件可以包括第一导电区域和介于其之间的沟道区域的第二导电区域。 微电极具有设置在沟道区域上并由至少一个电介质层分离的沟道区域控制部件。 通道区域控制部件具有从用作沟道区域控制部件的蚀刻掩模的光致抗蚀剂特征的非线性结构特性导出的非线性结构特性。
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2.发明授权Method of lithographic image alignment for use with a dual mask exposure technique 有权用于双掩模曝光技术的平版印刷图像对准方法公开(公告)号：US07108946B1
公开(公告)日：2006-09-19
申请号：US10755664
申请日：2004-01-12
申请人： Todd P. Lukanc , Sarah N. McGowan , Bhanwar Singh , Joerg Reiss
发明人： Todd P. Lukanc , Sarah N. McGowan , Bhanwar Singh , Joerg Reiss
CPC分类号： G03F9/7084 , G03F7/70633 , G03F7/70675
摘要： Methods of fabricating an integrated circuit on a wafer using dual mask exposure lithography is disclosed. Improved mask image alignment between a first mask image and a second mask image of a dual mask exposure technique can be achieved by aligning the second mask image to a latent image created by an exposure using the first mask image.
摘要翻译： 公开了使用双掩模曝光光刻在晶片上制造集成电路的方法。 可以通过使用第一掩模图像将第二掩模图像与由曝光产生的潜像对准来实现双掩模曝光技术的第一掩模图像和第二掩模图像之间的改进的掩模图像对准。
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3.发明授权Device and method for determining an illumination intensity profile of an illuminator for a lithography system 有权用于确定光刻系统的照明器的照明强度分布的装置和方法公开(公告)号：US07027130B2
公开(公告)日：2006-04-11
申请号：US10833651
申请日：2004-04-28
IPC分类号： G03B27/72
CPC分类号： G03F7/7085 , G03F7/70133 , G03F7/70441 , G03F7/70666 , G03F7/70941
摘要： A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.
摘要翻译： 一种用于产生形成投影光刻系统的一部分的照明器的照明强度分布的系统和方法。 来自照明器的辐射被投射到具有多个孔的照明轮廓掩模，使得每个孔通过辐射的不同部分。 检测并组装每个不同部分的辐射的强度以形成照射强度分布。
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4.发明授权公开(公告)号：US07071085B1
公开(公告)日：2006-07-04
申请号：US10852876
申请日：2004-05-25
IPC分类号： H01L21/475
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , Y10S438/947
摘要： The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.
摘要翻译： 本发明包括一种制造这种设备的装置和方法，包括以下步骤：形成待图案化的层，在待图案化的层上形成感光层，使光敏层形成图案，形成包括水平线和垂直线 将图案转移到待图案化的层上，在图案上形成第二感光层，图案化第二感光层以形成包括在水平线和垂直线之间对准的空间的第二图案，并且转印 第二图案到要被图案化的层以形成包括水平线和在其间具有空间的垂直线的第三图案，该空间包括在光刻的分辨率极限下可实现的宽度尺寸。
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5.发明授权Reduce line end pull back by exposing and etching space after mask one trim and etch 有权通过在掩模一次修整和蚀刻后曝光和蚀刻空间来减少线端拉回公开(公告)号：US07015148B1
公开(公告)日：2006-03-21
申请号：US10852883
申请日：2004-05-25
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0276 , H01L21/28123 , H01L21/28282 , H01L21/32139
摘要： The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension. The method includes the steps of: forming a photosensitive layer to be patterned, patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween, transferring the pattern to at least one underlying layer using the patterned photosensitive layer, forming a second photosensitive layer over the patterned at least one underlying layer, patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer, and transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension.
摘要翻译： 本发明是制造半导体器件和这种半导体器件的方法。 半导体器件包括集成电路图案，其包括水平线，垂直线和它们之间的空间，该空间包括精确的宽度尺寸。 该方法包括以下步骤：形成待图案化的感光层，图案化感光层以形成包括主水平线和主垂直线的图案，其间没有间隙，使用图案化将图案转移到至少一个下层 在所述图案化的至少一个下层上形成第二感光层，对所述第二感光层进行图案化，以形成第二图案，所述第二图案包括对准以剖开在所述至少一个下层中形成的水平线和垂直线的主空间， 以及将所述第二图案转移到所述至少一个下层，以形成包括水平线和在其间具有空间的垂直线的第三图案，所述空间包括精确的宽度尺寸。
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6.发明授权Lithographic photomask and method of manufacture to improve photomask test measurement 失效平版印刷光掩模和制造方法以改进光掩模测试测量公开(公告)号：US06974652B1
公开(公告)日：2005-12-13
申请号：US10699748
申请日：2003-11-03
摘要： A photomask for use in a lithographic process and a method of making a photomask are disclosed. A mask blank including a substrate, a sacrificial conductive layer disposed over the substrate and a radiation shielding layer disposed over the sacrificial conductive layer can be provided. Structures are then formed from the radiation shielding layer to define a pattern. Measurement of parameters associated with the structures are made with a measurement tool and, during the measuring, the sacrificial conductive layer provides a conductive plane to dissipate charge transferred to the mask by the measurement tool.
摘要翻译： 公开了用于光刻工艺的光掩模和制造光掩模的方法。 可以提供包括衬底，设置在衬底上的牺牲导电层和设置在牺牲导电层上方的辐射屏蔽层的掩模坯料。 然后从辐射屏蔽层形成结构以限定图案。 使用测量工具测量与结构相关的参数，并且在测量期间，牺牲导电层提供导电平面以消散由测量工具传递到掩模的电荷。
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7.发明授权System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法公开(公告)号：US07269804B2
公开(公告)日：2007-09-11
申请号：US10816764
申请日：2004-04-02
申请人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译： 选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。 对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。 可以选择提供最佳可制造性的RET。 以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。
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公开(公告)号：US06818358B1
公开(公告)日：2004-11-16
申请号：US10016439
申请日：2001-12-11
IPC分类号： G03F900
CPC分类号： G03F1/30
摘要： An exemplary Full Phase patterning method involves patterning gates to increase process margins from conventional methods. This technique can define all poly patterns with a phase mask, using only a field or trim mask to resolve conflicts in the phase mask. The trim mask exposes a series of lines that either separates the different phase areas where patterns not desired or minimizes the range of sizes of the phase patterns next to a critical gate area.
摘要翻译： 示例性的全相图案化方法包括图案化门以增加与常规方法的工艺裕度。 该技术可以使用相位掩模定义所有多边形图案，只使用字段或修剪蒙版来解决相位掩码中的冲突。 修剪掩模暴露一系列线，其中分离不期望的图案的不同相位区域，或者使关键栅极区域旁边的相位图案的尺寸范围最小化。
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公开(公告)号：US06514802B2
公开(公告)日：2003-02-04
申请号：US10054149
申请日：2002-01-22
申请人： Todd P. Lukanc , Kurt O. Taylor
发明人： Todd P. Lukanc , Kurt O. Taylor
IPC分类号： H01L2100
CPC分类号： H01L21/743 , H01L21/265 , H01L21/28525 , H01L21/3065 , H01L21/31155 , H01L21/326 , H01L21/76804 , H01L21/76825 , H01L21/76831 , H01L27/1203
摘要： A method for making frontside contact to a substrate through an SOI structure thereon is provided. An etching step is undertaken to form a trench in the SOI structure so as to expose and define a rug surface of the substrate. Then, a thin insulating layer, for example SiO2, is formed over the exposed surface of the substrate, this insulating layer being irregular because of its formation over the relatively rough etched surface. Contact material is provided in the trench, and electrical potential is applied across the contact and substrate sufficient to increase the conductivity of the insulating layer, i.e., to break down the insulating layer. Nitrogen may be implanted into the exposed surface of the substrate to slow subsequent growth of the insulating layer, resulting in an even thinner insulating layer, i.e., one even less resistant to breakdown upon application of electrical potential thereacross. If the insulating layer thereon is sufficiently thin or irregular, ohmic contact may be achieved between the contact and substrate without the application of such electrical potential. In yet another embodiment, prior to formation of the insulating layer, the exposed surface of the substrate and wall of the trench are fabricated such that meet at an abrp angle. Insulating material formed in ths area is of poor quality, readily lending itself to breakdown upon application of electrical potential across the contact material and substrate.
摘要翻译： 提供了一种通过其上的SOI结构使基板前侧接触的方法。 进行蚀刻步骤以在SOI结构中形成沟槽，以暴露和限定衬底的表面。 然后，在衬底的暴露表面上形成例如SiO2的薄绝缘层，由于其在相对粗糙的蚀刻表面上形成，该绝缘层是不规则的。 接触材料设置在沟槽中，并且跨接触和基底施加电势足以增加绝缘层的导电性，即分解绝缘层。 可以将氮气注入到衬底的暴露表面中以减缓绝缘层的随后生长，导致更薄的绝缘层，即，在施加电位之后甚至更不易于击穿。 如果其上的绝缘层足够薄或不规则，则可以在接触和衬底之间实现欧姆接触而不施加这种电势。 在另一个实施例中，在形成绝缘层之前，制造衬底的暴露表面和沟槽的壁，使得以一定的角度相遇。 形成在该区域中的绝缘材料质量差，容易借助于跨接触材料和基底施加电位而发生故障。
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公开(公告)号：US06448164B1
公开(公告)日：2002-09-10
申请号：US09716216
申请日：2000-11-21
IPC分类号： H01L213205
CPC分类号： H01L21/0274 , H01L21/28123
摘要： A method of forming either a gate pattern or a line pattern in a resist by using a dark field mask and a combination of a negative photoresist and a positive photoresist. The dark field mask is used to create a hole within the positive photoresist, by exposing only a portion of the positive photoresist to light, and then by subjecting the positive photoresist to a developer. The negative photoresist is formed within the hole of the positive photoresist, and etched or polished so that it is only disposed within the hole. The negative photoresist and the positive photoresist are subjected to a flood light exposure, and then to a developer. This causes the positive photoresist to dissolve, leaving the negative photoresist, thereby providing a very-small-dimension resist pattern that can be used to form either a gate or a line for a semiconductor device.
摘要翻译： 通过使用暗场掩模和负光致抗蚀剂和正性光致抗蚀剂的组合在抗蚀剂中形成栅极图案或线图案的方法。 暗场掩模用于在正性光致抗蚀剂中产生孔，通过仅将一部分正性光致抗蚀剂暴露于光，然后通过使正性光致抗蚀剂经受显影剂。 负光致抗蚀剂形成在正性光致抗蚀剂的孔内，并被蚀刻或抛光，使得其仅设置在孔内。 对负性光致抗蚀剂和正性光致抗蚀剂进行泛光曝光，然后进行显影。 这导致正性光致抗蚀剂溶解，留下负性光致抗蚀剂，从而提供可用于形成半导体器件的栅极或线的非常小的抗蚀剂图案。
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