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公开(公告)号：US20050212146A1
公开(公告)日：2005-09-29
申请号：US11054039
申请日：2005-02-08
申请人： Toshikazu Imaoka , Takeshi Yamaguchi , Ryosuke Usui , Hiroyuki Watanabe , Toshimichi Naruse , Atsushi Kato
发明人： Toshikazu Imaoka , Takeshi Yamaguchi , Ryosuke Usui , Hiroyuki Watanabe , Toshimichi Naruse , Atsushi Kato
IPC分类号： H01L23/28 , H01L21/44 , H01L21/56 , H01L23/31 , H01L25/065
CPC分类号： H01L21/565 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/01079 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor pellet and chip components are provided on an insulating substrate, and are sealed with a molding resin that is molded by transfer molding. The chip components are positioned so as to surround the semiconductor pellet on all four sides. The lengthwise directions of the chip components surrounding the semiconductor pellet are aligned in a uniform direction. The insulating substrate is set within a die molding apparatus so that during resin injection, the lengthwise directions of the chip components are aligned substantially perpendicularly to the direction of flow of the injected resin.
摘要翻译： 半导体芯片和芯片部件设置在绝缘基板上，并用通过传递模塑成型的模制树脂密封。 芯片部件被定位成围绕半导体芯片四周。 围绕半导体芯片的芯片部件的长度方向在均匀的方向上排列。 将绝缘基板设置在模具成型装置内，使得在树脂注入期间，芯片部件的长度方向基本上垂直于注入树脂的流动方向排列。
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公开(公告)号：US07709941B2
公开(公告)日：2010-05-04
申请号：US11054039
申请日：2005-02-08
申请人： Toshikazu Imaoka , Takeshi Yamaguchi , Ryosuke Usui , Hiroyuki Watanabe , Toshimichi Naruse , Atsushi Kato
发明人： Toshikazu Imaoka , Takeshi Yamaguchi , Ryosuke Usui , Hiroyuki Watanabe , Toshimichi Naruse , Atsushi Kato
IPC分类号： H01L23/02
CPC分类号： H01L21/565 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/01079 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor pellet and chip components are provided on an insulating substrate, and are sealed with a molding resin that is molded by transfer molding. The chip components are positioned so as to surround the semiconductor pellet on all four sides. The lengthwise directions of the chip components surrounding the semiconductor pellet are aligned in a uniform direction. The insulating substrate is set within a die molding apparatus so that during resin injection, the lengthwise directions of the chip components are aligned substantially perpendicularly to the direction of flow of the injected resin.
摘要翻译： 半导体芯片和芯片部件设置在绝缘基板上，并用通过传递模塑成型的模制树脂密封。 芯片部件被定位成围绕半导体芯片四周。 围绕半导体芯片的芯片部件的长度方向在均匀的方向上排列。 将绝缘基板设置在模具成型装置内，使得在树脂注入期间，芯片部件的长度方向基本上垂直于注入树脂的流动方向排列。
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公开(公告)号：US08110895B2
公开(公告)日：2012-02-07
申请号：US12789341
申请日：2010-05-27
IPC分类号： H01L27/08
CPC分类号： H01L23/49838 , H01F17/0006 , H01L23/49822 , H01L23/645 , H01L25/0657 , H01L2224/32145 , H01L2225/06568 , H01L2924/1305 , H01L2924/13091 , H01L2924/3011 , H05K1/0218 , H05K1/165 , H05K3/4685 , H05K2201/0715 , H01L2924/00
摘要： A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
摘要翻译： 电路基板结构中的第一布线层设置有第一电感器和第二电感器。 电介质层设置有分别电连接到第一电感器和第二电感器的第一通孔和第二通孔。 第二布线层设置有：电连接第一通孔和第二通孔的桥; 以及设置在桥周围的导电图案，导电图案的外边缘位于第一布线图案的外边缘的外侧，第二布线图案位于第一布线层的外侧。 桥作为共面线，抑制电磁场的产生。
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公开(公告)号：US07468645B2
公开(公告)日：2008-12-23
申请号：US11045936
申请日：2005-01-28
IPC分类号： H01P3/08
CPC分类号： H01P3/088 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H05K1/0219 , H05K1/024 , H05K1/141 , H05K3/222 , H05K3/28 , H05K3/3442 , H05K3/3452 , H05K3/4688 , H05K2201/2036 , H01L2924/00 , H01L2924/00014
摘要： A signal line circuit device is disposed on top of a mounting substrate. The signal line circuit device comprises a dielectric layer, a signal line formed on one surface of the dielectric layer, and a spacer (formed from a solder or a photo solder resist), which is formed between the mounting substrate and the dielectric layer, and generates a space separation between the signal line and the mounting substrate.
摘要翻译： 信号线电路装置设置在安装基板的顶部。 信号线电路装置包括介电层，形成在电介质层的一个表面上的信号线，以及形成在安装基板和电介质层之间的间隔物（由焊料或光阻焊剂形成），以及 在信号线和安装基板之间产生间隔。
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公开(公告)号：US20060170071A1
公开(公告)日：2006-08-03
申请号：US11336091
申请日：2006-01-20
申请人： Toshikazu Imaoka , Tetsuro Sawai , Atsushi Saita , Takeshi Yamaguchi , Makoto Tsubonoya , Kazunari Kurokawa
发明人： Toshikazu Imaoka , Tetsuro Sawai , Atsushi Saita , Takeshi Yamaguchi , Makoto Tsubonoya , Kazunari Kurokawa
IPC分类号： H01L29/00
CPC分类号： H01L23/49838 , H01F17/0006 , H01L23/49822 , H01L23/645 , H01L25/0657 , H01L2224/32145 , H01L2225/06568 , H01L2924/1305 , H01L2924/13091 , H01L2924/3011 , H05K1/0218 , H05K1/165 , H05K3/4685 , H05K2201/0715 , H01L2924/00
摘要： A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: abridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
摘要翻译： 电路基板结构中的第一布线层设置有第一电感器和第二电感器。 电介质层设置有分别电连接到第一电感器和第二电感器的第一通孔和第二通孔。 第二布线层设置有：电连接第一通孔和第二通孔的电路; 以及设置在桥周围的导电图案，导电图案的外边缘位于第一布线图案的外边缘的外侧，第二布线图案位于第一布线层的外侧。 桥作为共面线，抑制电磁场的产生。
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公开(公告)号：US20100315790A1
公开(公告)日：2010-12-16
申请号：US12789341
申请日：2010-05-27
CPC分类号： H01L23/49838 , H01F17/0006 , H01L23/49822 , H01L23/645 , H01L25/0657 , H01L2224/32145 , H01L2225/06568 , H01L2924/1305 , H01L2924/13091 , H01L2924/3011 , H05K1/0218 , H05K1/165 , H05K3/4685 , H05K2201/0715 , H01L2924/00
摘要： A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
摘要翻译： 电路基板结构中的第一布线层设置有第一电感器和第二电感器。 电介质层设置有分别电连接到第一电感器和第二电感器的第一通孔和第二通孔。 第二布线层设置有：电连接第一通孔和第二通孔的桥; 以及设置在桥周围的导电图案，导电图案的外边缘位于第一布线图案的外边缘的外侧，第二布线图案位于第一布线层的外侧。 桥作为共面线，抑制电磁场的产生。
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公开(公告)号：US07750434B2
公开(公告)日：2010-07-06
申请号：US11336091
申请日：2006-01-20
申请人： Toshikazu Imaoka , Tetsuro Sawai , Atsushi Saita , Takeshi Yamaguchi , Makoto Tsubonoya , Kazunari Kurokawa
发明人： Toshikazu Imaoka , Tetsuro Sawai , Atsushi Saita , Takeshi Yamaguchi , Makoto Tsubonoya , Kazunari Kurokawa
IPC分类号： H01L27/08
CPC分类号： H01L23/49838 , H01F17/0006 , H01L23/49822 , H01L23/645 , H01L25/0657 , H01L2224/32145 , H01L2225/06568 , H01L2924/1305 , H01L2924/13091 , H01L2924/3011 , H05K1/0218 , H05K1/165 , H05K3/4685 , H05K2201/0715 , H01L2924/00
摘要： A first wiring layer in a circuit substrate structure is provided with a first inductor and a second inductor. A dielectric layer is provided with a first via and a second via electrically connected to the first inductor and the second inductor, respectively. A second wiring layer is provided with: a bridge electrically connecting the first via and the second via; and a conductive pattern provided around the bridge, the outer edge of the conductive pattern being located outside the outer edge of the first wiring pattern and the second wiring pattern in the first wiring layer. The bridge functions as a coplanar line and suppresses generation of electromagnetic field.
摘要翻译： 电路基板结构中的第一布线层设置有第一电感器和第二电感器。 电介质层设置有分别电连接到第一电感器和第二电感器的第一通孔和第二通孔。 第二布线层设置有：电连接第一通孔和第二通孔的桥; 以及设置在桥周围的导电图案，导电图案的外边缘位于第一布线图案的外边缘的外侧，第二布线图案位于第一布线层的外侧。 该桥作为共面线，抑制电磁场的产生。
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公开(公告)号：US20050168304A1
公开(公告)日：2005-08-04
申请号：US11045936
申请日：2005-01-28
CPC分类号： H01P3/088 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H05K1/0219 , H05K1/024 , H05K1/141 , H05K3/222 , H05K3/28 , H05K3/3442 , H05K3/3452 , H05K3/4688 , H05K2201/2036 , H01L2924/00 , H01L2924/00014
摘要： A signal line circuit device is disposed on top of a mounting substrate. The signal line circuit device comprises a dielectric layer, a signal line formed on one surface of the dielectric layer, and a spacer (formed from a solder or a photo solder resist), which is formed between the mounting substrate and the dielectric layer, and generates a space separation between the signal line and the mounting substrate.
摘要翻译： 信号线电路装置设置在安装基板的顶部。 信号线电路装置包括介电层，形成在电介质层的一个表面上的信号线，以及形成在安装基板和电介质层之间的间隔物（由焊料或光阻焊剂形成），以及 在信号线和安装基板之间产生间隔。
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公开(公告)号：US11159030B2
公开(公告)日：2021-10-26
申请号：US15911308
申请日：2018-03-05
申请人： Takeshi Yamaguchi
发明人： Takeshi Yamaguchi
摘要： A battery pack includes a secondary battery, a secondary battery protecting integrated circuit configured to protect the secondary battery, at least one sensor configured to output a fault signal indicating sensing of a fault in the battery pack or an electronic apparatus including the battery pack, a detecting circuit configured to output a fault detection signal indicating a detection of the fault signal, a delay circuit configured to output a pulse delaying from the fault detection signal, and a counter configured to count a number of generating the pulse, the counter having at least N bits (N is an integer greater than 1), wherein the counter stops an operation until a count of 2(N-1).
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10.发明授权Apparatus, method, and non-transitory computer readable medium to achieve appropriate color reproduction characteristics 有权装置，方法和非暂时的计算机可读介质，以实现适当的色彩再现特性公开(公告)号：US08842335B2
公开(公告)日：2014-09-23
申请号：US12831653
申请日：2010-07-07
申请人： Takeshi Yamaguchi
发明人： Takeshi Yamaguchi
IPC分类号： H04N1/60
CPC分类号： H04N1/6088 , H04N1/6097
摘要： Disclosed is an information processing apparatus including: a control section to obtain output condition information to show an output condition when a color chart is output, to obtain colorimetric data obtained by measuring the color chart, to create a color conversion profile based on the obtained colorimetric data, and to embed the output condition information in the created color conversion profile according to an order determined in advance.
摘要翻译： 公开了一种信息处理设备，包括：控制部分，用于获得输出条件信息，以便在输出彩色图表时显示输出条件，以获得通过测量色彩图得到的色度数据，以便根据获得的色度产生颜色转换曲线 数据，并且根据预先确定的顺序将输出条件信息嵌入到所创建的颜色转换简档中。
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