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公开(公告)号:US20200068721A1
公开(公告)日:2020-02-27
申请号:US16672512
申请日:2019-11-03
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Wang-Hsiang TSAI , Cheng-Ta KO
IPC: H05K3/40 , H05K1/18 , H05K1/11 , H05K1/14 , H01L23/14 , H01L23/15 , H01L23/498 , H01L21/48 , H01L21/768
Abstract: A package structure, includes a metal layer, an insulating composite layer disposed thereon, a sealant bonded on the insulating composite layer, a chip embedded in the sealant, a circuit layer structure disposed on the sealant and the chip, and a protecting layer. The chip has a plurality of electrode pads exposed from the sealant. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has a plurality of conductive blind vias. The dielectric layer and the sealant are made of the same material. The circuit layer is disposed on the dielectric layer and extends into the conductive blind vias, and the bottommost circuit layer is electrically connected to the electrode pads through the conductive blind vias. The protecting layer is formed on the circuit layer structure and has a plurality of openings exposing a portion of the circuit layer structure.
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公开(公告)号:US20220131054A1
公开(公告)日:2022-04-28
申请号:US17102458
申请日:2020-11-24
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Tzu-Nien LEE
Abstract: A light-emitting package includes a black encapsulating member, a plurality of light-emitting components and a circuit structure. The black encapsulating member has a first surface and a second surface opposite to the first surface. The light-emitting components are embedded in the black encapsulating member. Each light-emitting component has a light-emitting surface, a back surface opposite to the light-emitting surface, and a plurality of pads disposed on the back surface. The light-emitting surface of each light-emitting component is exposed on the first surface and is flush with the first surface. The pads of each light-emitting component are exposed on the second surface. The circuit structure is disposed on the second surface and electrically connected to the pads.
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公开(公告)号:US20190239362A1
公开(公告)日:2019-08-01
申请号:US16379816
申请日:2019-04-10
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Cheng-Ta KO , John Hon-Shing LAU , Yu-Hua CHEN , Tzyy-Jang TSENG
IPC: H05K3/40 , H05K1/14 , H05K1/11 , H01L23/14 , H01L23/15 , H01L23/498 , H01L21/48 , H01L21/768 , H05K1/18
CPC classification number: H05K3/4038 , H01L21/4846 , H01L21/76898 , H01L23/147 , H01L23/15 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/131 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/014 , H01L2924/15311 , H05K1/11 , H05K1/112 , H05K1/142 , H05K1/183 , H05K2201/10674 , Y10T29/4913 , Y10T29/49146 , Y10T29/49165
Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.
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公开(公告)号:US20190098746A1
公开(公告)日:2019-03-28
申请号:US16203636
申请日:2018-11-29
Applicant: Unimicron Technology Corp.
Inventor: Ra-Min TAIN , Kai-Ming YANG , Chien-Tsai LI
Abstract: A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.
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公开(公告)号:US20240377598A1
公开(公告)日:2024-11-14
申请号:US18213142
申请日:2023-06-22
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor: Chin-Sheng WANG , Kai-Ming YANG , Chen-Hao LIN , Pu-Ju LIN
IPC: G02B6/42
Abstract: A co-packaged structure for optics and electrics includes a substrate, an optical module and an electrical connection layer. The optical module includes a carrier and an optical transceiver unit. The carrier is mounted on the substrate. The optical module is mounted on the carrier. The electrical connection layer is mounted on the substrate, and the carrier is electrically connected with a circuitry on the substrate through the electrical connection layer. A plurality of fiber accommodation through hole are formed on the substrate and correspond to the optical transceiver unit.
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公开(公告)号:US20220375919A1
公开(公告)日:2022-11-24
申请号:US17818006
申请日:2022-08-08
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Cheng-Ta KO , John Hon-Shing LAU , Yu-Hua CHEN , Tzyy-Jang TSENG
IPC: H01L25/00 , H01L21/48 , H01L23/538 , H01L23/00
Abstract: A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.
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公开(公告)号:US20220139886A1
公开(公告)日:2022-05-05
申请号:US17125981
申请日:2020-12-17
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Chia-Hao CHANG , Tzu-Nien LEE
IPC: H01L25/075 , H01L33/54 , H01L33/62
Abstract: A light-emitting package includes an encapsulating member, a plurality of light-emitting components disposed in the encapsulating member, a plurality of first electrode pads, a plurality of second electrode pads, and a plurality of conductive connection structures. The encapsulating member has a first surface and a second surface opposite to each other. Each light-emitting component has a light-emitting surface exposed on the first surface. Both the first electrode pads and the second electrode pads are exposed on the second surface. A first bonding surface of each first electrode pad and a second bonding surface of each second electrode pad are both flush with the second surface. The light-emitting components disposed on the first electrode pads are electrically connected to the first electrode pads. The conductive connection structures passing through the encapsulating member are electrically connected to the light-emitting components and the second electrode pads.
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公开(公告)号:US20220061157A1
公开(公告)日:2022-02-24
申请号:US17022128
申请日:2020-09-16
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Bo-Cheng LIN
Abstract: A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.
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公开(公告)号:US20210195761A1
公开(公告)日:2021-06-24
申请号:US17194323
申请日:2021-03-08
Applicant: Unimicron Technology Corp.
Inventor: Kai-Ming YANG , Chen-Hao LIN , Wang-Hsiang TSAI , Cheng-Ta KO
IPC: H05K3/40 , H01L21/768 , H01L21/48 , H05K1/11 , H05K1/18 , H05K1/14 , H01L23/14 , H01L23/15 , H01L23/498 , H01L23/36 , H01L23/538 , H05K3/46 , H01L23/00 , H01L21/683
Abstract: A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.
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公开(公告)号:US20190373713A1
公开(公告)日:2019-12-05
申请号:US16543609
申请日:2019-08-18
Applicant: Unimicron Technology Corp.
Inventor: Tzyy-Jang TSENG , Kai-Ming YANG , Pu-Ju LIN , Cheng-Ta KO , Yu-Hua CHEN
Abstract: A stacked structure includes a circuit board, an electronic component, metallic cores, and insulating cladding layers. The circuit board includes first bonding pads. The electronic component includes second bonding pads that are opposite to the first bonding pads. Each metallic core is connected to a corresponding first bonding pad and a corresponding second bonding pad. The metallic cores have a curved surface interposed between the corresponding first bonding pad and the corresponding second bonding pad. The insulating cladding layers are separated from each other and cover the curved surfaces of the metallic cores.
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