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14 条记录 (耗时 0.013 秒)

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200185597A1

    公开(公告)日：2020-06-11

    申请号：US16216969

    申请日：2018-12-11

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kun-Ju Li ,  Hsin-Jung Liu ,  I-Ming Tseng ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Fu-Chun Hsiao ,  Hui-Lin Wang ,  Tzu-Hsiang Hung ,  Chih-Yueh Li ,  Ang Chan ,  Jing-Yin Jhang

    IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

    摘要： A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

    Method of fabricating fin structure
    2.
    发明授权
    Method of fabricating fin structure 有权

    公开(公告)号：US09966263B1

    公开(公告)日：2018-05-08

    申请号：US15587228

    申请日：2017-05-04

    申请人： United Microelectronics Corp.

    发明人： Kun-Ju Li ,  Li-Chieh Hsu ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Chih-Hsun Lin ,  Hsin-Jung Liu

    IPC分类号： H01L21/033

    CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

    摘要： A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.

    Alignment mark structure and method of fabricating the same
    3.
    发明授权
    Alignment mark structure and method of fabricating the same 有权

    公开(公告)号：US11145602B2

    公开(公告)日：2021-10-12

    申请号：US16786919

    申请日：2020-02-10

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

    IPC分类号： H01L23/544 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    摘要： An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

    Method for fabricating a semiconductor device
    6.
    发明授权
    Method for fabricating a semiconductor device 有权

    公开(公告)号：US11482666B2

    公开(公告)日：2022-10-25

    申请号：US17023382

    申请日：2020-09-17

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Hsin-Jung Liu ,  Chau-Chung Hou ,  Ang Chan ,  Kun-Ju Li ,  Wen-Chin Lin

    IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

    摘要： A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
    7.
    发明申请
    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220085284A1

    公开(公告)日：2022-03-17

    申请号：US17023382

    申请日：2020-09-17

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Hsin-Jung Liu ,  Chau-Chung Hou ,  Ang Chan ,  Kun-Ju Li ,  Wen-Chin Lin

    IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

    摘要： A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    ALIGNMENT MARK STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210249357A1

    公开(公告)日：2021-08-12

    申请号：US16786919

    申请日：2020-02-10

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kun-Ju Li ,  Jhih-Yuan Chen ,  Hsin-Jung Liu ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Fu-Chun Hsiao ,  Ji-Min Lin ,  Chun-Han Chen

    IPC分类号： H01L23/544 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

    摘要： An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer are independently comprises silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

    Manufacturing method of memory device
    10.
    发明授权
    Manufacturing method of memory device 有权

    公开(公告)号：US10804461B1

    公开(公告)日：2020-10-13

    申请号：US16517693

    申请日：2019-07-22

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Hsin-Jung Liu ,  Kun-Ju Li ,  Ang Chan ,  Chau-Chung Hou ,  Yu-Lung Shih

    IPC分类号： H01L21/00 ,  H01L43/12 ,  H01L43/02

    摘要： A method for manufacturing a memory device is provided, the method includes the following steps: firstly, providing a dielectric layer, then simultaneously forming a contact window and an alignment mark trench in the dielectric layer, wherein the contact window exposes a lower metal line, then forming a conductive layer on the surface of the dielectric layer, in the contact window and in the alignment mark trench, performing a planarization step on the conductive layer, and leaving a residue in the alignment mark trench. Subsequently, a nitrogen plasma step (N2 plasma) is performed on the dielectric layer, a cleaning step is performed to remove the residue in the alignment mark trench, and a patterned magnetic tunneling junction, MTJ) film is laminated on the contact window.