公开(公告)号：US20230082279A1

公开(公告)日：2023-03-16

申请号：US17990755

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shing Chen

IPC: H01L27/146 ,  H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/49

Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer and first conductive metal layer on the first polysilicon plug; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in the first ILD layer and second conductive metal layer on the second polysilicon plug.

公开(公告)号：US09490360B2

公开(公告)日：2016-11-08

申请号：US14183541

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Shing Chen ,  Ming-Hui Chang ,  Wei-Ting Wu ,  Ying-Chou Lai ,  Horng-Nan Chern ,  Chorng-Lih Young ,  Chin-Sheng Yang

IPC: H01L21/761 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7835

Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

Abstract translation: 提供一种半导体器件，包括P型衬底，P型第一阱区，N型第二阱区，栅极，N型源极和漏极区，虚拟栅极和N型阱阱区域 。 第一阱区位于衬底中。 第二阱区位于靠近第一阱区的衬底中。 栅极位于基板上并且覆盖第一阱区域的一部分和第二阱区域的一部分。 源极区位于栅极一侧的第一阱区中。 漏极区域位于栅极另一侧的第二阱区域中。 虚拟栅极位于栅极和漏极区域之间的衬底上。 深井区域位于基板中并围绕第一和第二井区域。 还提供了一种半导体器件的操作方法。

公开(公告)号：US09379237B1

公开(公告)日：2016-06-28

申请号：US14602282

申请日：2015-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hui Chang ,  Wei-Ting Wu ,  Ming-Shing Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36

CPC classification number: H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835

Abstract: A LDMOS includes a gate structure disposed on the surface of a semiconductor substrate, a source region having a first conductivity type, a drain region having the first conductivity type, an isolation region surrounding the source/drain regions, a doped region having a second conductivity type, and a base region having the second conductivity type formed in the doped region. The source/drain regions are respectively disposed on two sides of the gate structure. The doped region surrounds the isolation region, and the bottom of the doped region is deeper than the bottom of the isolation region. The base region is disposed at the surface of the semiconductor substrate.

Abstract translation: LDMOS包括设置在半导体衬底的表面上的栅极结构，具有第一导电类型的源极区域，具有第一导电类型的漏极区域，围绕源极/漏极区域的隔离区域，具有第二导电性的掺杂区域 并且在掺杂区域中形成具有第二导电类型的基极区域。 源极/漏极区域分别设置在栅极结构的两侧。 掺杂区域围绕隔离区域，并且掺杂区域的底部比隔离区域的底部更深。 基极区域设置在半导体衬底的表面。

公开(公告)号：US20160372554A1

公开(公告)日：2016-12-22

申请号：US15252246

申请日：2016-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shing Chen ,  Wei-Ting Wu ,  Ming-Hui Chang ,  Chao-Chun Ning

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.

Abstract translation: 提供了包括衬底，第二深阱，栅极，源极，漏极和第一掺杂剂区域的横向扩散的金属氧化物半导体器件。 衬底包括具有第一导电类型的第一深阱。 具有第二导电类型的第二深阱设置在第一深孔中。 栅极设置在基板和第一和第二深井的边界上。 具有第二导电类型的源极和漏极分别设置在栅极旁边和第一深阱以及第二深阱的旁边。 具有第一导电类型的第一掺杂区域设置在第二深阱中，其中第一掺杂区域与漏极分离。 此外，还提供了制造所述横向扩散金属氧化物半导体器件的方法。

公开(公告)号：US09385236B1

公开(公告)日：2016-07-05

申请号：US14748240

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Ming-Shing Chen ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  G06F17/50

CPC classification number: H01L29/7853 ,  G06F17/5081 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7856

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plurality of fin shaped structures and a dummy gate structure. The fin shaped structures are disposed in a substrate, where at least one of the fin shaped structures has a tipped end. The dummy gate structure is disposed on the substrate, and includes an extending portion covering the tipped end.

Abstract translation: 半导体器件及其形成方法，半导体器件包括多个鳍状结构和虚拟栅极结构。 翅片状结构设置在基板中，其中至少一个翅片形结构具有尖端。 虚拟栅极结构设置在基板上，并且包括覆盖端部的延伸部分。

公开(公告)号：US20150103585A1

公开(公告)日：2015-04-16

申请号：US14051471

申请日：2013-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Young-Ran Chuang ,  Chao-Hsien Wu ,  Ming-Shing Chen

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C7/04

Abstract: A Static Random Access Memory (SRAM) cell is a latch circuit formed with two inverters each formed with a PMOS transistor and an NMOS transistor. The latch circuit is coupled to a capacitor through a switch. When the switch is switched on, the stability of data stored in the SRAM cell will be enhanced. When the switch is switched off, data can be written to the SRAM cell quickly.

Abstract translation: 静态随机存取存储器（SRAM）单元是形成有两个反相器的锁存电路，每个反相器都形成有PMOS晶体管和NMOS晶体管。 锁存电路通过开关耦合到电容器。 当开关打开时，SRAM单元中存储的数据的稳定性将得到提高。 当开关关闭时，数据可以快速写入SRAM单元。

公开(公告)号：US20210217798A1

公开(公告)日：2021-07-15

申请号：US16794233

申请日：2020-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shing Chen

IPC: H01L27/146

Abstract: An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer, first self-aligned silicide layer on the polysilicon plug and first conductive metal layer on the first self-aligned silicide layer; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in first ILD layer, second self-aligned silicide layer on the second polysilicon plug, and second conductive metal layer on the second self-aligned silicide layer.

公开(公告)号：US09780171B2

公开(公告)日：2017-10-03

申请号：US15252246

申请日：2016-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shing Chen ,  Wei-Ting Wu ,  Ming-Hui Chang ,  Chao-Chun Ning

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/1083 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.

公开(公告)号：US20150236150A1

公开(公告)日：2015-08-20

申请号：US14183541

申请日：2014-02-19

Applicant: United Microelectronics Corp.

Inventor： Ming-Shing Chen ,  Ming-Hui Chang ,  Wei-Ting Wu ,  Ying-Chou Lai ,  Horng-Nan Chern ,  Chorng-Lih Young ,  Chin-Sheng Yang

IPC: H01L29/78 ,  H01L29/45 ,  H03K3/012 ,  H01L29/10 ,  H01L29/49 ,  H01L29/788 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7835

Abstract: Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

Abstract translation: 提供一种半导体器件，包括P型衬底，P型第一阱区，N型第二阱区，栅极，N型源极和漏极区，虚拟栅极和N型阱阱区域 。 第一阱区位于衬底中。 第二阱区位于靠近第一阱区的衬底中。 栅极位于基板上并且覆盖第一阱区域的一部分和第二阱区域的一部分。 源极区位于栅极一侧的第一阱区中。 漏极区域位于栅极另一侧的第二阱区域中。 虚拟栅极位于栅极和漏极区域之间的衬底上。 深井区域位于基板中并围绕第一和第二井区域。 还提供了一种半导体器件的操作方法。

公开(公告)号：US20150123197A1

公开(公告)日：2015-05-07

申请号：US14071674

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shing Chen ,  Wei-Ting Wu ,  Ming-Hui Chang ,  Chao-Chun Ning

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided. The substrate includes a first deep well having a first conductive type. The second deep well having a second conductive type is disposed in the first deep well. The gate is disposed on the substrate and the boundary of the first and the second deep well. The source and the drain having a second conductive type are disposed beside the gate and in the first deep well and the second deep well respectively. The first dopant region having a first conductive type is disposed in the second deep well, wherein the first dopant region is separated from the drain. Moreover, a method for fabricating said lateral-diffused metal oxide semiconductor device is also provided.

Abstract translation: 提供了包括衬底，第二深阱，栅极，源极，漏极和第一掺杂剂区域的横向扩散的金属氧化物半导体器件。 衬底包括具有第一导电类型的第一深阱。 具有第二导电类型的第二深阱设置在第一深孔中。 栅极设置在基板和第一和第二深井的边界上。 具有第二导电类型的源极和漏极分别设置在栅极旁边和第一深阱以及第二深阱的旁边。 具有第一导电类型的第一掺杂区域设置在第二深阱中，其中第一掺杂区域与漏极分离。 此外，还提供了制造所述横向扩散金属氧化物半导体器件的方法。