公开(公告)号：US20240097038A1

公开(公告)日：2024-03-21

申请号：US17964925

申请日：2022-10-13

Applicant: United Microelectronics Corp.

Inventor： Yi Chuen Eng ,  Tzu-Feng Chang ,  Teng-Chuan Hu ,  Yi-Wen Chen ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/66795

Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

公开(公告)号：US10177132B2

公开(公告)日：2019-01-08

申请号：US15088122

申请日：2016-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: G06F17/50 ,  H01L27/02 ,  G03F1/36 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.

公开(公告)号：US20170243861A1

公开(公告)日：2017-08-24

申请号：US15088122

申请日：2016-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1104

Abstract: A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.

公开(公告)号：US20240161818A1

公开(公告)日：2024-05-16

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: G11C11/412 ,  H01L27/1104 ,  H01L29/6681 ,  H01L29/7851

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

公开(公告)号：US20190067268A1

公开(公告)日：2019-02-28

申请号：US16171339

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/419 ,  H01L27/1104

Abstract: The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.

公开(公告)号：US12224001B2

公开(公告)日：2025-02-11

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

公开(公告)号：US10396064B2

公开(公告)日：2019-08-27

申请号：US16171339

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.

公开(公告)号：US20160099184A1

公开(公告)日：2016-04-07

申请号：US14509032

申请日：2014-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chun-Chieh Chang ,  Tzu-Feng Chang ,  Po-Peng Lin

IPC: H01L21/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/11

CPC classification number: H01L22/14 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1104

Abstract: A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a first scale value are obtained. Plural second transistors are formed and a second VtMM value and a second scale value are obtained. Plural third transistors are formed and a third VtMM value and a third scale value are obtained. A first channel length of the first transistor is smaller than a second channel length of the second transistor and is equal to a third channel length of the third transistor. A VtMM v.s. scale figure is established. A line is formed by linking the first dot and the third dot and a vertical Gap between the line and the second dot is measured. The capability of the semiconductor system is determined based on the vertical Gap. The invention further provides a chip.

Abstract translation: 提供了一种估计半导体制造系统的能力的方法。 形成多个第一晶体管，并获得第一VtMM值和第一刻度值。 形成多个第二晶体管，并获得第二VtMM值和第二刻度值。 形成多个第三晶体管，并获得第三VtMM值和第三比例值。 第一晶体管的第一沟道长度小于第二晶体管的第二沟道长度，并且等于第三晶体管的第三沟道长度。 VtMM v.s. 规模建立。 通过连接第一点和第三点形成线，并且测量线与第二点之间的垂直间隙。 基于垂直间隙确定半导体系统的能力。 本发明还提供一种芯片。