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    Method of forming semiconductor device
    5.
    发明授权
    Method of forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号：US09443952B2

    公开(公告)日：2016-09-13

    申请号：US14506009

    申请日：2014-10-03

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Tsen Lu ,  Chih-Jung Su ,  Jian-Wei Chen ,  Shui-Yen Lu ,  Yi-Wen Chen ,  Po-Cheng Huang ,  Chen-Ming Huang ,  Shih-Fang Tzou

    IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/4966 ,  H01L29/517

    Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构，并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分，直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。

    Semiconductor device and manufacturing method thereof
    6.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US09312356B1

    公开(公告)日：2016-04-12

    申请号：US14613379

    申请日：2015-02-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ching-Ling Lin ,  Chih-Sen Huang ,  Yi-Wen Chen

    IPC: H01L21/70 ,  H01L29/49 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/28

    CPC classification number: H01L29/4966 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628

    Abstract: The semiconductor device includes a gate electrode, a first interlayer dielectric, a first mask layer, a second mask layer and a second interlayer dielectric. The first interlayer dielectric surrounds the periphery of the gate electrode, and the first mask layer is disposed on the gate electrode. The first mask layer and the gate electrode have at least one same metal component. The second mask layer is disposed on the sidewalls of the first mask layer, and the second interlayer dielectric is disposed on the second mask layer and in direct contact with the first interlayer dielectric.

    Abstract translation: 半导体器件包括栅电极，第一层间电介质，第一掩模层，第二掩模层和第二层间电介质。 第一层间电介质围绕栅电极的周边，并且第一掩模层设置在栅电极上。 第一掩模层和栅电极具有至少一个相同的金属成分。 第二掩模层设置在第一掩模层的侧壁上，第二层间电介质设置在第二掩模层上并与第一层间电介质直接接触。

    Semiconductor structure and manufacturing method of the same
    7.
    发明授权
    Semiconductor structure and manufacturing method of the same 有权
    半导体结构及其制造方法相同

    公开(公告)号：US09231071B2

    公开(公告)日：2016-01-05

    申请号：US14187701

    申请日：2014-02-24

    Applicant: United Microelectronics Corp.

    Inventor： Hung-Yi Wu ,  Chien-Ming Lai ,  Yi-Wen Chen

    IPC: H01L21/44 ,  H01L21/70 ,  H01L29/49 ,  H01L29/40

    CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

    Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

    Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括隔离层，栅介质层，第一功函数金属，第一底阻挡层，第二功函数金属和第一顶阻挡层。 隔离层形成在衬底上并具有第一栅极沟槽。 栅介质层形成在第一栅极沟槽中。 第一功函数金属形成在第一栅极沟槽中的栅介质层上。 第一底部阻挡层形成在第一功函数金属上。 第二功能金属形成在第一底部阻挡层上。 第一顶部阻挡层形成在第二功函数金属上。

    METHOD FOR PHYSICALLY UNCLONABLE FUNCTION THROUGH GATE HEIGHT TUNING
    8.
    发明申请
    METHOD FOR PHYSICALLY UNCLONABLE FUNCTION THROUGH GATE HEIGHT TUNING 有权

    公开(公告)号：US20250017003A1

    公开(公告)日：2025-01-09

    申请号：US18230174

    申请日：2023-08-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chang-Yih Chen ,  Yi-Wen Chen ,  Wei-Chung Sun

    IPC: H10B20/00 ,  G06F21/75

    Abstract: A method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a CMP process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture PIO pairs in an internal bias generator. Since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed I/O (PIO) pairs becomes larger, so as to achieve random code generation in physically unclonable function (PUF).

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20160099179A1

    公开(公告)日：2016-04-07

    申请号：US14506009

    申请日：2014-10-03

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Tsen Lu ,  Chih-Jung Su ,  Jian-Wei Chen ,  Shui-Yen Lu ,  Yi-Wen Chen ,  Po-Cheng Huang ,  Chen-Ming Huang ,  Shih-Fang Tzou

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105

    CPC classification number: H01L29/66545 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/4966 ,  H01L29/517

    Abstract: A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

    Abstract translation: 公开了一种形成半导体器件的方法。 提供具有多个翅片的基板。 绝缘层填充两个相邻翅片之间的间隙的下部。 在一个翅片上形成至少一个第一堆叠结构，并且在一个绝缘层上形成至少一个第二堆叠结构。 形成第一电介质层以覆盖第一和第二堆叠结构。 去除第一电介质层的一部分和第一和第二堆叠结构的部分。 去除第一电介质层的另一部分，直到剩余的第一电介质层的顶部低于第一和第二堆叠结构的顶部。 形成第二电介质层以覆盖第一和第二堆叠结构。 去除第二电介质层的一部分直到第一和第二堆叠结构的顶部露出。

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