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    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200185597A1

    公开(公告)日：2020-06-11

    申请号：US16216969

    申请日：2018-12-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  I-Ming Tseng ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Fu-Chun Hsiao ,  Hui-Lin Wang ,  Tzu-Hsiang Hung ,  Chih-Yueh Li ,  Ang Chan ,  Jing-Yin Jhang

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

    Method of fabricating fin structure
    2.
    发明授权
    Method of fabricating fin structure 有权

    公开(公告)号：US09966263B1

    公开(公告)日：2018-05-08

    申请号：US15587228

    申请日：2017-05-04

    Applicant: United Microelectronics Corp.

    Inventor： Kun-Ju Li ,  Li-Chieh Hsu ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Chih-Hsun Lin ,  Hsin-Jung Liu

    IPC: H01L21/033

    CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

    Abstract: A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.

    Method for fabricating a semiconductor device
    7.
    发明授权
    Method for fabricating a semiconductor device 有权

    公开(公告)号：US11482666B2

    公开(公告)日：2022-10-25

    申请号：US17023382

    申请日：2020-09-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Jung Liu ,  Chau-Chung Hou ,  Ang Chan ,  Kun-Ju Li ,  Wen-Chin Lin

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

    Abstract: A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220085284A1

    公开(公告)日：2022-03-17

    申请号：US17023382

    申请日：2020-09-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Jung Liu ,  Chau-Chung Hou ,  Ang Chan ,  Kun-Ju Li ,  Wen-Chin Lin

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

    Abstract: A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
    9.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20250096000A1

    公开(公告)日：2025-03-20

    申请号：US18487141

    申请日：2023-10-16

    Applicant: United Microelectronics Corp.

    Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  Jhih Yuan Chen ,  I-Ming Lai ,  Ang Chan ,  Wei Xin Gao ,  Hsiang Chi Chien ,  Hao-Che Hsu ,  Chau Chung Hou ,  Zong Sian Wu

    IPC: H01L21/304 ,  H01L21/306 ,  H01L21/762

    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.

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