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    DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS
    3.
    发明申请
    DUMMY PATTERNS AND METHOD FOR GENERATING DUMMY PATTERNS 有权
    DUMMY PATTERNS和生成DUMMY PATTERNS的方法

    公开(公告)号：US20140042636A1

    公开(公告)日：2014-02-13

    申请号：US14064219

    申请日：2013-10-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

    IPC: H01L23/48

    CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

    Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.

    Abstract translation: 一种用于产生虚拟图案的方法包括提供具有第一密度的布局图案的布局区域，在布局图案中插入具有与第一密度对应的第二密度的多个第一伪图案，将布局区域分成多个子图 具有第三密度的区域，根据第二密度和第三密度之间的差来调整第一伪图案的尺寸，并将布局图案和第一伪图案输出到光掩模上。

    MAGNETORESISTIVE RANDOM ACCESS MEMORY
    7.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20210184104A1

    公开(公告)日：2021-06-17

    申请号：US17182146

    申请日：2021-02-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

    IPC: H01L43/02 ,  G11C11/16 ,  H01L27/02 ,  H01L27/22

    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

    METHOD FOR CHECKING DIE SEAL RING ON LAYOUT AND COMPUTER SYSTEM
    10.
    发明申请
    METHOD FOR CHECKING DIE SEAL RING ON LAYOUT AND COMPUTER SYSTEM 有权
    在布局和计算机系统上检查DIE密封圈的方法

    公开(公告)号：US20130326436A1

    公开(公告)日：2013-12-05

    申请号：US13951095

    申请日：2013-07-25

    Applicant: United Microelectronics Corp.

    Inventor： Jui-Yun Chang ,  Jian-Cheng Chen ,  I-Jen Kao ,  Chih-Wei Hsu

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received. A checking process is performed according to the digital database of the layout and the tape-out information and, meanwhile, a mask design procedure for designing a mask pattern corresponding to the layout is performed by using the digital database of the layout, the text information and the tape-out information. A result of the checking process is recorded in an inspection table corresponding to the layout.

    Abstract translation: 本发明涉及一种用于在布局上检查模具密封环的方法。 该方法包括以下步骤：接收与至少具有对应于布局的文本信息的设备对应的布局的数字数据库。 接收与布局相对应的磁带输出信息。 根据布局的数字数据库和输出信息进行检查处理，同时，通过使用布局的数字数据库，文本信息来执行用于设计与布局相对应的掩模图案的掩模设计过程 和输出信息。 检查处理的结果记录在与布局对应的检查表中。

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