公开(公告)号：US09502285B1

公开(公告)日：2016-11-22

申请号：US14733930

申请日：2015-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0334 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.

Abstract translation: 提供了一种形成沟槽的方法。 在基板上形成第一层，第二层和第三层。 形成具有多个第三沟槽的图案化第三层。 间隔件形成在第三沟槽的侧壁上，接着通过去除第三沟槽之间的图案化第三层的一部分。 通过使用间隔物和图案化的第三层作为掩模，形成具有多个第二沟槽的图案化的第二层。 接下来，完全去除图案化的第三层和间隔物，并且在图案化的第二层上形成阻挡层，填充到至少一个第二沟槽中，以将所述第二沟槽分成至少两个部分。 通过使用图案化的第二层和阻挡层作为掩模来对第一层进行构图，以形成具有第一沟槽的图案化的第一层。

公开(公告)号：US08765495B1

公开(公告)日：2014-07-01

申请号：US13863397

申请日：2013-04-16

Applicant: United Microelectronics Corp.

Inventor： Yi-Hsiu Lee ,  Guo-Xin Hu ,  Qiao-Yuan Liu ,  Yen-Sheng Wang

IPC: H01L21/00

CPC classification number: H01L21/266 ,  G03F1/36 ,  G03F7/70441 ,  H01L21/26513 ,  H01L21/28123

Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.

Abstract translation: 形成掺杂区域图案的方法包括以下步骤。 首先，将包括栅极布局图案和掺杂区域布局图案的器件布局图案提供给计算机系统。 随后，器件布局图案被分割成多个子区域，并且子区域具有不同的栅极布局图案的图案密度。 然后，分别对每个子区域中的掺杂区域布局图案进行至少光学邻近校正（OPC）计算，以分别在每个子区域中形成校正的子掺杂区域布局图案。 之后，校正的子掺杂区域布局图案被组合以形成校正的掺杂区域布局图案，并且通过计算机系统将校正的掺杂区域布局图案输出到掩模上。

公开(公告)号：US10969687B2

公开(公告)日：2021-04-06

申请号：US16209871

申请日：2018-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Kai-Ming Liu ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: G03F7/20 ,  H01L21/3213 ,  H01L21/027

Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.

公开(公告)号：US20190187562A1

公开(公告)日：2019-06-20

申请号：US16209871

申请日：2018-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Kai-Ming Liu ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/3213

CPC classification number: G03F7/2022 ,  H01L21/027 ,  H01L21/3213

Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.

公开(公告)号：US20210202492A1

公开(公告)日：2021-07-01

申请号：US17202359

申请日：2021-03-16

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.

公开(公告)号：US20190189620A1

公开(公告)日：2019-06-20

申请号：US16177348

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L27/10885 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.

公开(公告)号：US09530731B2

公开(公告)日：2016-12-27

申请号：US14607051

申请日：2015-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Wen Fang ,  Chin-Lung Lin ,  Kuo-Chang Tien ,  Yi-Hsiu Lee ,  Chien-Hsiung Wang

IPC: G03F1/00 ,  G06F17/50 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  G03F1/144 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077 ,  G06T2207/30148 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension.

Abstract translation: 由计算机系统执行的用于修改线路图案的光学邻近校正的方法包括以下步骤。 首先，提供具有与平行线图案相对布置的平行线图案和互连图案的集成电路布局。 然后，使用计算机基于互连图案的位置来修改集成电路布局，以便分别在每个平行线图案的两侧上产生凸部和凹部。 在凸部和凹部之前和之后的线图案的部分是直线并且具有相同的临界尺寸。

公开(公告)号：US08977988B2

公开(公告)日：2015-03-10

申请号：US13859718

申请日：2013-04-09

Applicant: United Microelectronics Corp.

Inventor： Kuan-Wen Fang ,  Chin-Lung Lin ,  Kuo-Chang Tien ,  Yi-Hsiu Lee ,  Chien-Hsiung Wang

IPC: G06F17/50 ,  G06K9/00

CPC classification number: H01L23/528 ,  G03F1/144 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077 ,  G06T2207/30148 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern.

Abstract translation: 由计算机系统执行的光学邻近校正方法和由其形成的集成电路布局的方法，光学邻近校正步骤包括：提供具有多条平行线图案的集成电路布局，其中至少一条线图案的一侧 设置有凸部; 以及通过在所述线图案的另一侧形成与所述凸部对应的凹部来修改所述集成电路布局。

公开(公告)号：US20140304666A1

公开(公告)日：2014-10-09

申请号：US13859718

申请日：2013-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Wen Fang ,  Chin-Lung Lin ,  Kuo-Chang Tien ,  Yi-Hsiu Lee ,  Chien-Hsiung Wang

IPC: G06F17/50

CPC classification number: H01L23/528 ,  G03F1/144 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077 ,  G06T2207/30148 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern.

Abstract translation: 由计算机系统执行的光学邻近校正方法和由其形成的集成电路布局的方法，光学邻近校正步骤包括：提供具有多条平行线图案的集成电路布局，其中至少一条线图案的一侧 设置有凸部; 以及通过在所述线图案的另一侧形成与所述凸部对应的凹部来修改所述集成电路布局。

公开(公告)号：US11800702B2

公开(公告)日：2023-10-24

申请号：US17202359

申请日：2021-03-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H10B12/00 ,  H01L21/308 ,  H01L21/762

CPC classification number: H10B12/482 ,  H01L21/3086 ,  H01L21/76224 ,  H10B12/053 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.