公开(公告)号：US11856771B2

公开(公告)日：2023-12-26

申请号：US17864435

申请日：2022-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren

IPC: H10B43/20 ,  H01L29/78 ,  H01L29/66 ,  H10B41/20

CPC classification number: H10B43/20 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/20

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11882699B2

公开(公告)日：2024-01-23

申请号：US17224100

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren

IPC: H10B43/20 ,  H01L29/78 ,  H01L29/66 ,  H10B41/20

CPC classification number: H10B43/20 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/20

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11699730B2

公开(公告)日：2023-07-11

申请号：US17510371

申请日：2021-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Xiaojuan Gao ,  Chi Ren

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

公开(公告)号：US20200373436A1

公开(公告)日：2020-11-26

申请号：US16452311

申请日：2019-06-25

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren

IPC: H01L29/792 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66

Abstract: A structure of a memory device and a fabrication method thereof are provided. The structure of the memory device includes a tunneling layer disposed on a substrate. A first oxide/nitride/oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.

公开(公告)号：US12185532B2

公开(公告)日：2024-12-31

申请号：US18365243

申请日：2023-08-04

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

Abstract: A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.

公开(公告)号：US11765893B2

公开(公告)日：2023-09-19

申请号：US17331319

申请日：2021-05-26

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H10B41/30 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

CPC classification number: H10B41/30 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.

公开(公告)号：US20210280590A1

公开(公告)日：2021-09-09

申请号：US17331319

申请日：2021-05-26

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.

公开(公告)号：US11056495B2

公开(公告)日：2021-07-06

申请号：US16455297

申请日：2019-06-27

Applicant: United Microelectronics Corp.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Qiuji Zhao ,  Boon Keat Toh

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/51 ,  H01L29/423

Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.

公开(公告)号：US12057481B2

公开(公告)日：2024-08-06

申请号：US18199967

申请日：2023-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Xiaojuan Gao ,  Chi Ren

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

公开(公告)号：US11943920B2

公开(公告)日：2024-03-26

申请号：US17468637

申请日：2021-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Zhiguo Li ,  Chi Ren ,  Xiaojuan Gao ,  Boon Keat Toh

IPC: H01L27/11531 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B41/42 ,  H10B43/40

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H10B43/40

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.