公开(公告)号：US06251744B1

公开(公告)日：2001-06-26

申请号：US09356870

申请日：1999-07-19

申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L2176

CPC分类号： H01L21/76213

摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

摘要翻译： 在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。 在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。 去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。 牺牲氧化物层沉积在半导体衬底的表面上。 在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

公开(公告)号：US06130168A

公开(公告)日：2000-10-10

申请号：US349844

申请日：1999-07-08

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/32 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/105 ,  H01L21/302

CPC分类号： H01L27/11526 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/954

摘要： A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer. A second polysilicon layer is deposited over the ONO layer in the memory area, over the thin gate oxide layer in the low voltage area, and over the thick gate oxide layer in the high voltage area. The second polysilicon layer, ONO layer and first polysilicon layer in the memory cell area are patterned to form a control gate overlying a floating gate separated by the ONO layer. The second polysilicon layer is patterned to form a low voltage transistor in the low voltage area and a high voltage transistor in the high voltage area.

摘要翻译： 描述了为高压和低压晶体管形成差分栅极氧化物厚度的新方法。 提供半导体衬底，其中衬底的有源区域通过浅沟槽隔离区域与其它有源区域隔离。 沉积在衬底表面上的隧道氧化物层上的多晶硅层。 去除多晶硅和隧道氧化物层，除了在存储单元区域中。 沉积在存储单元区域中的多晶硅层和低电压和高电压区域的衬底表面上的ONO层。 在高电压区域中去除ONO层。 衬底在高压区域被氧化以形成厚的栅极氧化物层。 此后，在低电压区域中去除ONO层，并且衬底被氧化以形成薄的栅极氧化物层。 第二多晶硅层沉积在存储区域中的ONO层上，在低电压区域的薄栅极氧化物层上方，以及高电压区域中的厚栅极氧化物层上方。 将存储单元区域中的第二多晶硅层，ONO层和第一多晶硅层图案化以形成覆盖由ONO层分离的浮动栅极的控制栅极。 将第二多晶硅层图案化以在低电压区域中形成低压晶体管，并在高电压区域形成高压晶体管。

公开(公告)号：US6001687A

公开(公告)日：1999-12-14

申请号：US283849

申请日：1999-04-01

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8239

CPC分类号： H01L27/11521

摘要： When FLASH cells are made in association with STI (as opposed to LOCOS) it is often the case that stringers of silicon nitride are left behind after the spacers have been formed. This problem has been eliminated by requiring that the oxide in the STI trenches remain in place at the time that the silicon nitride spacers are formed. After that, the oxide is removed in the usual manner, following which a SALICIDE process is used to form a self aligned source line. When this sequence is followed no stringers are left behind on the walls of the trench, guaranteeing the absence of any open circuits or high resistance regions in the source line.

摘要翻译： 当与STI（与LOCOS相反）制成FLASH单元时，通常在形成间隔物之后留下氮化硅桁条。 通过要求在形成氮化硅间隔物的时刻STI槽中的氧化物保持在适当位置，已经消除了这个问题。 之后，以通常的方式去除氧化物，随后使用SALICIDE工艺来形成自对准的源极线。 当遵循该顺序时，沟槽的壁上不留下桁条，保证在源极线中不存在任何开路或高电阻区域。

公开(公告)号：US06348382B1

公开(公告)日：2002-02-19

申请号：US09392391

申请日：1999-09-09

申请人： Hung-Der Su ,  Chrong Jung Lin ,  Jong Chen ,  Wen-Ting Chu

发明人： Hung-Der Su ,  Chrong Jung Lin ,  Jong Chen ,  Wen-Ting Chu

IPC分类号： H01L218234

CPC分类号： H01L21/823857 ,  H01L21/823814

摘要： A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.

摘要翻译： 提供了一种新的方法，由此使用一个处理顺序创建用于HV CMOS器件和LV CMOS器件的LDD区域。 用于高电压和低电压器件的栅电极都在硅衬底的表面上产生。 高压LDD（HVLDD）与HV CMOS栅电极自对准，对HV和LV CMOS器件进行栅极退火。 低压LDD（LVLDD）与LV CMOS栅电极自对准。 在CMOS器件的栅电极完成之后，形成栅极间隔物，源极/漏极注入和CMOS器件所需的后端处理。

公开(公告)号：US06297098B1

公开(公告)日：2001-10-02

申请号：US09431236

申请日：1999-11-01

申请人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

发明人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/26586

摘要： A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

摘要翻译： 公开了一种用于在闪速存储器应用中用于非易失性存储器和DDD（双掺杂漏极）的高压器件中形成LDD（轻掺杂漏极）的方法。 高压器件通过以倾斜角度使用两个连续的离子注入形成，其提供了接合点附近的掺杂分布的改进的灰度级，并且在更高的电压下提高了结点击穿。 层叠闪存单元中的双掺杂漏极也通过两次注入形成，但是以最佳倾角形成，其中第一次注入被轻掺杂，而第二次重掺杂。 由此产生的DDD提供更快的编程速度，减少编程电流，增加读取电流和减少闪存单元中的漏极干扰。

公开(公告)号：US06465836B2

公开(公告)日：2002-10-15

申请号：US09821199

申请日：2001-03-29

申请人： Chrong Jung Lin ,  Sheng-Wei Tsao ,  Di-Son Kuo ,  Jack Yeh ,  Wen-Ting Chu ,  Chung-Li Chang ,  Chia-Ta Hsieh

发明人： Chrong Jung Lin ,  Sheng-Wei Tsao ,  Di-Son Kuo ,  Jack Yeh ,  Wen-Ting Chu ,  Chung-Li Chang ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L29/7887 ,  H01L29/42336

摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.

摘要翻译： 在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，在半导体衬底内形成沟槽，其沟槽内的沟槽区域完全包含在分离栅极场内 效应晶体管（FET）器件。 类似地，在分裂栅极场效应晶体管内还形成有沟槽内的浮置栅电极，并且在沟槽内覆盖沟道区的下部子部分。 最后，浮栅电极依次形成在沟槽内垂直和水平重叠的覆盖通道的上部子部分的控制栅电极。 分离栅场效应晶体管（FET）器件制造具有增强的面密度和增强的性能。

公开(公告)号：US06544828B1

公开(公告)日：2003-04-08

申请号：US10044860

申请日：2001-11-07

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chrong-Jung Lin ,  Sheng-Wei Tsaur

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chrong-Jung Lin ,  Sheng-Wei Tsaur

IPC分类号： H01L218234

CPC分类号： H01L29/402 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/4238

摘要： A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过在漏极侧的浅沟槽隔离区域的边缘处形成导电场板来提高高电压NMOS器件的耐久性和鲁棒性的方法。 活性区域通过衬底中的隔离区域分离。 在活性区域上生长栅极氧化物层。 导电层沉积在栅极氧化物层上并被图案化以在有源区域中形成栅电极，并且在有源区域的漏极侧上的隔离边缘处形成与有源区域和隔离区域重叠的导电条带，其中导电条 在集成电路器件的制造中减小隔离边缘的电场。

公开(公告)号：US06420233B1

公开(公告)日：2002-07-16

申请号：US09766860

申请日：2001-01-19

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chung-Li Chang ,  Wen-Ting Chu ,  Chrong-Jung Lin

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chung-Li Chang ,  Wen-Ting Chu ,  Chrong-Jung Lin

IPC分类号： H01L29336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.

摘要翻译： 在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，采用掺杂多晶硅浮栅，其具有中间环状部分，其掺杂浓度高于周边环形 掺杂多晶硅浮栅电极的一部分。 掺杂多晶硅浮置栅电极的中心环形部分内的较高掺杂剂浓度提供了分裂栅极场效应晶体管（FET）器件的增强的编程速度特性。 在掺杂多晶硅浮置栅电极的外围环形部分内的较低掺杂剂浓度在分裂栅极场效应晶体管（FET）器件的制造的某些情况下在分裂栅极场效应晶体管（FET）器件内提供增强的擦除速度特性。

公开(公告)号：US06297099B1

公开(公告)日：2001-10-02

申请号：US09765045

申请日：2001-01-19

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jack Yeh ,  Chrong Jung Lin ,  Wen-Ting Chu ,  Chung-Li Chang

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jack Yeh ,  Chrong Jung Lin ,  Wen-Ting Chu ,  Chung-Li Chang

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  Y10S438/981

摘要： A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.

摘要翻译： 一种制造浮栅/字线装置的方法，包括以下步骤。 提供半导体结构。 在半导体结构上方形成浮栅部分。 浮动门部分具有侧壁和顶面。 多晶氧化物部分形成在浮动栅极的顶表面上。 在半导体结构，多晶氧化物部分和多晶氧化物部分之上形成多层氧化物层。 所述多晶硅氧化物层具有初始厚度，并且包括：与所述浮动栅极部分相邻的所述半导体结构的至少一部分上的字线区域部分; 浮动部分侧壁上的侧壁区域部分; 以及多个氧化物部分上方的顶部。 互折层氧化物层的顶部的初始厚度减小到第二厚度，而不会减小多晶氧化物字线区域部分的初始厚度或多余氧化物侧壁区域部分的明显部分。 在多晶硅层上形成多晶硅层。 将结构图案化以形成浮动栅/字线装置。

公开(公告)号：US06261905B1

公开(公告)日：2001-07-17

申请号：US09560625

申请日：2000-04-28

申请人： Jong Chen ,  Chrong-Jong Lin ,  Hung-Der Su ,  Wen-Ting Chu

发明人： Jong Chen ,  Chrong-Jong Lin ,  Hung-Der Su ,  Wen-Ting Chu

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell and the making thereof is disclosed where the cell has a damascene-like stacked gate. The stacked gate is formed not by blanket depositing a first polysilicon layer and then subtractively etching to form a floating gate followed by the depositing of a second polysilicon layer separated by an intervening inter-gate dielectric layer over the floating gate. On the contrary, a trench is formed in a nitride layer formed over a substrate using a modified damascene process. The first polysilicon layer is conformally deposited into the damascene-like trench to form the floating gate of the disclosed cell. Then, a layer of inter-gate dielectric layer is formed over the first polysilicon layer in the trench, followed by the forming of a second polysilicon layer over the dielectric layer, thus forming the damascene-like stacked gate of this invention. The disclosed method alleviates the problem of having poly residues resulting from defects caused by etching the conventionally deposited polysilicon layer. Furthermore, etching over active region can also cause damage to the underlying substrate, which is not the case here. In addition, the method enables the incorporation of the curved structure of the floating gate of this invention into the area that increases the coupling ratio of the flash memory cell.

摘要翻译： 公开了一种闪存单元及其制造方法，其中电池具有镶嵌式堆叠栅极。 层叠栅极不是通过覆盖沉积第一多晶硅层而形成的，然后进行减法蚀刻以形成浮置栅极，随后沉积由浮置栅极上的中间栅介质层分隔开的第二多晶硅层。 相反，使用改进的镶嵌工艺在形成在衬底上的氮化物层中形成沟槽。 第一多晶硅层被共形沉积到镶嵌状沟槽中以形成所公开电池的浮动栅极。 然后，在沟槽中的第一多晶硅层上方形成栅极间电介质层，随后在电介质层上形成第二多晶硅层，从而形成本发明的镶嵌层状堆叠栅极。 所公开的方法减轻了由通过蚀刻常规沉积的多晶硅层引起的缺陷产生的多余残留物的问题。 此外，在有源区上的蚀刻也可能对下面的衬底造成损害，这在这里不是这种情况。 此外，该方法使得能够将本发明的浮动栅极的弯曲结构结合到增加闪存单元的耦合比的区域中。