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    Method and apparatus for masking modulo exponentiation calculations in an integrated circuit
    4.
    发明授权
    Method and apparatus for masking modulo exponentiation calculations in an integrated circuit 失效
    用于掩蔽集成电路中的模幂运算的方法和装置

    公开(公告)号：US06064740A

    公开(公告)日：2000-05-16

    申请号：US969144

    申请日：1997-11-12

    申请人： Andreas Curiger ,  Wendell Little

    发明人： Andreas Curiger ,  Wendell Little

    IPC分类号： G06F7/72 ,  H04L9/00

    CPC分类号： G06F7/723 ,  G06F2207/7261

    摘要： Circuitry which performs modular mathematics to solve the equation C=M.sup.k mod n and n is performed in a manner to mask the exponent k's signature from timing or power monitoring attacks. The modular exponentation function is performed in a normalized manner such that binary ones and zeros in the exponent are calculated by being modulo-squared and modulo-multiplied.

    摘要翻译： 执行模块数学以求解方程C = Mk mod n和n的电路以从定时或功率监视攻击屏蔽指数k的签名的方式来执行。 模式指数函数以归一化方式执行，使得指数中的二进制1和零通过模平方和模乘而计算。

    Paging receiver with LPC speech synthesizer
    6.
    发明授权
    Paging receiver with LPC speech synthesizer 失效
    具有LPC语音合成器的寻呼接收机

    公开(公告)号：US4769642A

    公开(公告)日：1988-09-06

    申请号：US125794

    申请日：1987-11-27

    申请人： Walter L. Davis ,  Wendell Little

    发明人： Walter L. Davis ,  Wendell Little

    IPC分类号： G08B3/10 ,  H04W88/02 ,  H04B7/00 ,  H04Q7/02

    CPC分类号： H04W88/023 ,  G08B3/1033

    摘要： A paging receiver with an LPC speech synthesizer is described. The paging receiver of the present invention includes a controller and decoder, and a microprocessor controlled speech synthesizer both coupled to a dual port memory. Digitally encoded voice messages are stored in a dual port memory which includes a scratchpad area for storing control words and address pointers which indicate the attributes and location of stored digitally encoded voice messages. Messages are reconstructed by reading the control words and address pointers and processing the information stored in memory with a speech synthesizer. The structure is adapted to store and process LPC encoded signals and it permits a message to be stored while another is being reproduced. In addition, information contained in the control words permits old or read messages to be discarded if a new message must be stored.

    摘要翻译： 描述了具有LPC语音合成器的寻呼机。 本发明的寻呼机包括控制器和解码器以及耦合到双端口存储器的微处理器控制语音合成器。 数字编码语音消息存储在双端口存储器中，该双端口存储器包括用于存储控制字的暂存区域和指示所存储的数字编码语音消息的属性和位置的地址指针。 通过读取控制字和地址指针并用语音合成器处理存储在存储器中的信息来重建消息。 该结构适于存储和处理LPC编码信号，并且允许在另一个被再现时存储消息。 此外，如果必须存储新的消息，则控制字中包含的信息允许丢弃旧的或读取的消息。

    Clocking system for microcontrollers
    7.
    发明授权
    Clocking system for microcontrollers 失效
    微控制器的时钟系统

    公开(公告)号：US06167527A

    公开(公告)日：2000-12-26

    申请号：US364353

    申请日：1999-07-28

    申请人： Wendell Little ,  Stephen Grider ,  Joseph Triece

    发明人： Wendell Little ,  Stephen Grider ,  Joseph Triece

    IPC分类号： G06F1/08 ,  H03K19/003 ,  G06F1/12 ,  G06F1/04

    CPC分类号： G06F1/08 ,  H03K19/00361

    摘要： An improved clocking system for micro controllers is provided. The micro controller has two mechanisms by which the clocking is provided. One clock is provided by an external clock signal which is generally crystal controlled. A second mechanism for providing the clock is also present. This second clock can be useful as the "primary" or first clock which is generally a crystal oscillator may take several milliseconds to stabilize following a restart from a stop mode. The second clock mechanism can for example be an internal ring oscillator or other type of clock which although not as accurate as a crystal clock does not require the several milliseconds to recover.

    摘要翻译： 提供了一种用于微控制器的改进的计时系统。 微控制器具有提供时钟的两种机制。 一个时钟由通常是晶体控制的外部时钟信号提供。 还提供了提供时钟的第二种机制。 第二个时钟可以是有用的，因为通常是晶体振荡器的“初级”或第一时钟可能需要几毫秒才能在从停止模式重新启动之后稳定。 第二时钟机制可以例如是内部环形振荡器或其他类型的时钟，尽管不像晶体时钟那样精确地不需要几毫秒来恢复。

    Dual page memory system having storage elements which are selectively swapped between the pages
    8.
    发明授权
    Dual page memory system having storage elements which are selectively swapped between the pages 失效
    双页存储器系统具有有选择地在页之间交换的存储元件

    公开(公告)号：US4618946A

    公开(公告)日：1986-10-21

    申请号：US651028

    申请日：1984-09-17

    申请人： Wendell Little ,  Tim Williams

    发明人： Wendell Little ,  Tim Williams

    IPC分类号： G06F12/02 ,  G06F15/167 ,  G11C7/10 ,  G11C13/00

    CPC分类号： G11C7/1006 ,  G06F12/0284 ,  G06F15/167

    摘要： In a dual page memory system sharable by first and second processors, a plurality of storage elements are assigned to first and second pages accessible by the respective processor. An address decoder decodes addresses provided by either of the processors, and provides a selection signal corresponding to a predetermined storage element in each of the pages. A page selector couples the selection signal to the storage element in the page assigned to that processor. An access controller provides access to that processor to the storage element to which the selection is coupled. An assignment controller is provided to selectively swap corresponding storage elements between the pages.

    摘要翻译： 在由第一和第二处理器共享的双页存储器系统中，多个存储元件被分配给可由相应处理器访问的第一和第二页。 地址解码器对由任一个处理器提供的地址进行解码，并且提供与每个页面中的预定存储元件对应的选择信号。 页面选择器将选择信号耦合到分配给该处理器的页面中的存储元件。 访问控制器提供对该处理器的访问到选择所耦合的存储元件。 提供分配控制器以选择性地交换页之间的对应存储元件。