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1.发明授权Semiconductor memory with sequential clocked access codes for test mode entry 失效具有用于测试模式进入的顺序时钟访问代码的半导体存储器
公开(公告)号：US5072138A
公开(公告)日：1991-12-10
申请号：US570203
申请日：1990-08-17
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G06F11/22 , G11C7/10 , G11C29/00 , G11C29/14 , G11C29/46 , H01L21/66 , H01L27/10
CPC分类号： G11C29/46 , G01R31/31701 , G01R31/31719 , G11C7/1045
摘要： An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.
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2.发明授权Semiconductor memory with power-on reset controlled latched row line repeaters 失效半导体存储器具有上电复位控制锁存行行中继器
公开(公告)号：US5526318A
公开(公告)日：1996-06-11
申请号：US376127
申请日：1995-01-19
摘要： An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.
摘要翻译： 公开了一种集成电路存储器，其存储器阵列分为块或子阵列。 在每个子阵列之间放置有行行中继器，其将来自行解码器的行线或从先前的子阵列传送到下一个子阵列。 根据列地址的一部分来控制行行中继器，使得在整个所选行被通电之后，与选择的子阵列不相关联的那些行行中继器将在其输出处的行线断电 。 行行中继器各自包括锁存器，使得与选择的子阵列相关联的行行中继器将保持所选择的行线路通电。 公开了行行中继器电路的各种实施例。 还公开了从上电复位电路对行行中继器的进一步控制。 还公开了虚拟行线，其模拟实际的行线，使得所选择的行已被完全通电的时间更为公知。 因此，虚拟行线可以控制未选择的行行中继器使其输出断电的时间。
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公开(公告)号：US5124951A
公开(公告)日：1992-06-23
申请号：US588600
申请日：1990-09-26
摘要： An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.
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公开(公告)号：US5450019A
公开(公告)日：1995-09-12
申请号：US185650
申请日：1994-01-26
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.
摘要翻译： 公开了一种推挽输出驱动器电路，其包括用于控制驱动器晶体管的栅极以在周期开始时实现输出端子的预充电的控制电路。 预充电在每个周期开始时启动，例如由地址转换指示。 存储输出端的先前数据状态，并且通过启用具有滞后的门控电平检测器（例如施密特触发器）来驱动存储的先前数据状态的驱动晶体管，使相对的驱动器晶体管成为可能。 驱动存储的先前数据状态的晶体管被禁用，从而排除了预充电期间的振荡。 门控施密特触发器每个接收输出端子的电压，并且在使能时，接通将输出端子耦合到驱动晶体管的栅极的晶体管。 当输出端子达到中间电压时，施密特触发器也可以控制预充电，从而由于滞后特性使振荡最小化。 输出端子连接到预充电驱动晶体管的栅极有助于在预充电期间消除过冲。
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公开(公告)号：US5424985A
公开(公告)日：1995-06-13
申请号：US170612
申请日：1993-12-20
摘要： Circuits and methods for generating a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device is disclosed. In a first embodiment, a delay circuit is provided for generating an output clock signal for controlling a circuit internal to an integrated circuit, such as a clocked sense amplifier in a memory device, relative to an earlier timing signal, such as a row select signal. The delay circuit is implemented by components having their design parameters, such as transistor dimensions and transistor orientation, corresponding to elements in an active portion of the circuit, such as memory cell transistors. Process variations that affect the electrical properties and the speed of the transistors in the active portion of the circuit will similarly affect the electrical properties and speed of transistors in the delay circuit, so the delay circuit can track and automatically compensate for process-induced speed variations, eliminating the need for large design time margins. Alternative embodiments are also disclosed which account for the threshold voltage drops across pass transistors in a memory array, and mimic the memory cell read current, when generating a sense amplifier clock signal.
摘要翻译： 公开了用于产生延迟添加到半导体器件中将第一电路的输出计时到第二电路的输入的时钟信号的电路和方法。 在第一实施例中，提供延迟电路，用于产生用于控制集成电路内部的电路的输出时钟信号，诸如存储器件中的定时读出放大器相对于较早的定时信号，例如行选择信号 。 延迟电路由具有它们的设计参数（诸如晶体管尺寸和晶体管取向）的元件实现，对应于诸如存储单元晶体管的电路的有源部分中的元件。 影响电路的有效部分中的晶体管的电性能和速度的工艺变化将类似地影响延迟电路中的晶体管的电性能和速度，因此延迟电路可以跟踪并自动补偿工艺引起的速度变化 ，消除了对设计时间裕度大的需求。 还公开了替代实施例，其考虑了存储器阵列中跨越晶体管的阈值电压降，并且在产生读出放大器时钟信号时模拟存储器单元读取电流。
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6.发明授权Semiconductor memory with power-on reset controlled latched row line repeaters 失效具有上电复位控制的锁定线路重复器的半导体存储器
公开(公告)号：US5121358A
公开(公告)日：1992-06-09
申请号：US588609
申请日：1990-09-26
摘要： An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.
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公开(公告)号：US5517455A
公开(公告)日：1996-05-14
申请号：US220976
申请日：1994-03-31
CPC分类号： G11C29/785 , G11C29/24
摘要： Fuse circuitry is presented which emulates fuse blowing in a temporary manner. As an embodiment, redundant elements of an integrated circuit may be enabled and/or tested prior to laser repair through the use of non-destructive fuse circuitry which emulates fuse blowing. An integrated circuit has a plurality of addressable elements and a plurality of redundant elements, which may be used to replace defective addressable elements. Each redundant element has a non-destructive fuse circuit associated with it which may be used to enable and/or test the redundant element prior to laser repair by emulating the blowing of a fuse contained in the non-destructive fuse circuit. The non-destructive fuse circuit is comprised of a fuse connected to a control logic element, such as an inverter, wherein the control logic element is in turn controlled by a test signal. Emulation of blowing the fuse or not blowing the fuse is accomplished by the logic level of the test signal. So, rather than connecting the fuse to a power supply, the fuse is connected to the control logic element which is controlled by the test signal. Thus, non-destructive enabling and testing of a redundant element prior to laser repair may be accomplished by emulating blowing or not blowing of the fuse through the control logic element. The fuse can then be permanently blown if desired.
摘要翻译： 提供了以临时方式模拟保险丝熔断的保险丝电路。 作为实施例，集成电路的冗余元件可以在激光修复之前通过使用模拟保险丝熔断的非破坏性熔丝电路来启用和/或测试。 集成电路具有多个可寻址元件和多个冗余元件，其可用于替换不可寻址的元件。 每个冗余元件具有与其相关联的非破坏性熔丝电路，其可以用于在激光修复之前通过模拟非破坏性熔丝电路中包含的熔丝的熔化来启用和/或测试冗余元件。 非破坏性熔丝电路包括连接到控制逻辑元件（例如逆变器）的熔丝，其中控制逻辑元件又由测试信号控制。 对保险丝进行熔断或不熔断的模拟是通过测试信号的逻辑电平实现的。 因此，不是将保险丝连接到电源，而是将熔丝连接到由测试信号控制的控制逻辑元件。 因此，在激光修复之前的冗余元件的非破坏性使能和测试可以通过模拟通过控制逻辑元件的熔丝的吹送或不吹动来实现。 如果需要，保险丝可以永久吹塑。
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公开(公告)号：US5311467A
公开(公告)日：1994-05-10
申请号：US864481
申请日：1992-04-07
IPC分类号： G11C11/41 , G11C8/08 , G11C11/407 , G11B7/00
CPC分类号： G11C8/08
摘要： A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.
摘要翻译： 公开了一种存储器，其具有以行和列排列的存储器阵列中的多个存储器单元，每个存储器单元能够存储其中的逻辑状态。 每对位线与其中一列相关联。 列解码器响应于列地址选择数组中的列。 多个字线驱动器响应于行地址选择用于与其相关联的位线对连接的一行存储器单元。 多个行隔离电路响应于批量写入信号而隔离并使能来自行的其余部分的每行的选定组的存储单元。 每行隔离电路在其相关联的字线驱动器和相关联的行中的所选择的存储器单元之间具有传导路径。 批量写信号被发送到包含所选存储单元的每列。 然后响应于批量写入信号将第一逻辑状态写入所选择的存储器单元。
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公开(公告)号：US5408435A
公开(公告)日：1995-04-18
申请号：US984233
申请日：1992-11-20
申请人： David C. McClure , Thomas A. Coker
发明人： David C. McClure , Thomas A. Coker
CPC分类号： G11C29/46
摘要： An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.
摘要翻译： 具有正常操作模式和特殊操作模式的集成电路，例如特殊测试模式。 特殊测试模式通过一系列信号（例如终端的过电压偏移）而不是通过单个这样的偏移来实现，使得不经意地进入特殊测试模式的可能性较小，例如由于噪声或功率 降低和启动设备。 用于启用测试模式的电路包括一系列D型触发器，每个D型触发器在检测到过电压状态以及在另一个端子处施加的特定逻辑电平时被计时; 可以为多种特殊测试模式提供多个触发器系列。 附加功能包括提供上电复位电路，该电路在器件上电期间锁定进入测试模式。 进入测试模式的确认通过在器件未使能时在输出端子处呈现低阻抗来提供; 设备的芯片使能使设备退出测试模式。 一旦进入测试模式，器件的输出使能端可提供芯片使能功能。
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公开(公告)号：US5265100A
公开(公告)日：1993-11-23
申请号：US552567
申请日：1990-07-13
申请人： David C. McClure , Thomas A. Coker
发明人： David C. McClure , Thomas A. Coker
摘要： An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.
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