公开(公告)号：US10944414B1

公开(公告)日：2021-03-09

申请号：US16922873

申请日：2020-07-07

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  Bob W. Verbruggen ,  Christophe Erdmann

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/06

Abstract: An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.

公开(公告)号：US11923856B2

公开(公告)日：2024-03-05

申请号：US17713901

申请日：2022-04-05

Applicant: XILINX, INC.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann

IPC: H03K5/00 ,  H03K5/135 ,  H03K5/14 ,  H03K5/15 ,  H03K19/0948 ,  H03M1/82

CPC classification number: H03K5/14 ,  H03K5/135 ,  H03K5/15066 ,  H03K19/0948 ,  H03M1/82 ,  H03K2005/00026

Abstract: Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.

公开(公告)号：US10581450B1

公开(公告)日：2020-03-03

申请号：US16249230

申请日：2019-01-16

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  Bob W. Verbruggen ,  Christophe Erdmann ,  Roberto Pelliconi

IPC: H03M1/66 ,  H03G3/30 ,  H03F3/45

Abstract: Apparatus and associated methods relating to a digital-to-analog converter (DAC) include a programmable resistance network coupled between a voltage supply node VDD and a switch cell circuit to provide a predetermined resistance in response to the VDD and current IS of the switch cell circuit. In an illustrative example, the DAC may include a switch cell circuit comprising one or more switch cells connected in parallel. Each switch cell may include a differential gain circuit having a first branch coupled to a second branch at an input of a current source. The programmable resistance may include a variable resistance configured to adjust a voltage (Vbias) supplied to the switch cell circuit in response to a control signal. By introducing the programmable resistance network, predetermined bias and/or gain values may be dynamically adjusted with a constant board-level power supply VDD.

公开(公告)号：US11716089B1

公开(公告)日：2023-08-01

申请号：US17696734

申请日：2022-03-16

Applicant: XILINX, INC.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann

IPC: H03M1/06

CPC classification number: H03M1/0604 ,  H03M1/0682

Abstract: A biasing scheme for a voltage-to-time converter (VTC). An example biasing circuit generally includes a reference current source; a feedback loop current source; an amplifier having a first input coupled to a target voltage node, having a second input, and having an output coupled to a control input of the reference current source and to a control input of the feedback loop current source; a first capacitive element; a first switch coupled in parallel with the first capacitive element; a second switch coupled between the feedback loop current source and the first capacitive element; and a third switch coupled between the first capacitive element and the second input of the amplifier.

公开(公告)号：US10969821B2

公开(公告)日：2021-04-06

申请号：US15991179

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Ryan Kinnerk ,  Bob W. Verbruggen ,  John E. McGrath

IPC: G06F1/12 ,  G06F1/14 ,  G06F1/10

Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

公开(公告)号：US10886906B1

公开(公告)日：2021-01-05

申请号：US15989623

申请日：2018-05-25

Applicant: Xilinx, Inc.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann ,  Conrado K. Mesadri

IPC: H03K5/156 ,  G06F1/10

Abstract: A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.

公开(公告)号：US20200097038A1

公开(公告)日：2020-03-26

申请号：US15991179

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Ryan Kinnerk ,  Bob W. Verbruggen ,  John E. McGrath

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/14

Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

公开(公告)号：US10320401B2

公开(公告)日：2019-06-11

申请号：US15784022

申请日：2017-10-13

Applicant: Xilinx, Inc.

Inventor： Augusto R. Ximenes ,  Bob W. Verbruggen ,  Christophe Erdmann

IPC: H03L7/091 ,  H03L7/099

Abstract: An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

公开(公告)号：US11323108B1

公开(公告)日：2022-05-03

申请号：US17107572

申请日：2020-11-30

Applicant: XILINX, INC.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann ,  Ionut C. Cical

IPC: H04L25/02 ,  H03K5/133 ,  H03K3/037 ,  H05K1/02 ,  G06F13/40

Abstract: A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive− voltage, respectively. The circuit further includes a first diode connected transistor (“DCT”) coupled to the second input interface, a first switching transistor (“ST”) coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.

公开(公告)号：US11009597B2

公开(公告)日：2021-05-18

申请号：US16222801

申请日：2018-12-17

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  Christophe Erdmann ,  Bob W. Verbruggen

IPC: G01S13/50 ,  G01S13/90 ,  G01S13/58

Abstract: A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of analog-to-digital converters (ADCs) to sample the reflected pulses in response to the clock signal. Accordingly, the ADCs are locked in phase with the DACs.