公开(公告)号：US09859320B2

公开(公告)日：2018-01-02

申请号：US15393006

申请日：2016-12-28

Applicant: XINTEC INC.

Inventor： Shun-Wen Long ,  Guo-Jyun Chiou ,  Meng-Han Kuo ,  Ming-Chieh Huang ,  Hsi-Chien Lin ,  Chin-Kang Chen ,  Yi-Pin Chen

IPC: H01L27/14 ,  H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14698 ,  H01L2224/11

Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

公开(公告)号：US08748926B2

公开(公告)日：2014-06-10

申请号：US13720649

申请日：2012-12-19

Applicant: Xintec Inc.

Inventor： Kuo-Hua Liu ,  Yi-Ming Chang ,  Hsi-Chien Lin

IPC: H01L33/00 ,  H01L21/00

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/561 ,  H01L23/10 ,  H01L23/48 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.

Abstract translation: 芯片封装包括：具有第一和第二表面的衬底; 形成在基板上或设置在基板上的器件区域; 设置在所述第一表面上的电介质层; 至少一个导电焊盘，其布置在所述电介质层中并电连接到所述器件区域; 设置在所述电介质层上的平面层，其中所述平面层的上表面与所述导电焊盘之间的垂直距离大于约2μm; 设置在所述第一表面上的透明基板; 设置在所述透明基板和所述平面层之间的第一间隔层; 以及第二间隔层，其设置在所述透明基板和所述基板之间并且延伸到所述电介质层的与所述导电焊盘接触的开口中，其中所述第二间隔层和所述导电焊盘之间基本上没有间隙。

公开(公告)号：US09799778B2

公开(公告)日：2017-10-24

申请号：US15157776

申请日：2016-05-18

Applicant: XINTEC INC.

Inventor： Yi-Ying Kuo ,  Ming-Chieh Huang ,  Hsi-Chien Lin

IPC: H01L31/02 ,  H01L31/18 ,  H01L31/0216

CPC classification number: H01L31/02002 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/562 ,  H01L31/0216 ,  H01L31/186 ,  H01L2224/11

Abstract: A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface. The insulating layer covers the second surface and the side surface, and the flowing insulating material layer is disposed below the insulating layer, and the flowing insulating material layer has a trench exposing the conductive pad protruded form the side surface. The conductive layer is disposed below the flowing insulating material layer and extended into the trench to contact the conductive pad.

公开(公告)号：US09196589B2

公开(公告)日：2015-11-24

申请号：US13845728

申请日：2013-03-18

Applicant: Xintec Inc.

Inventor： Yu-Lin Yen ,  Hsi-Chien Lin ,  Yeh-Shih Ho

IPC: H01L29/06 ,  H01L23/00 ,  H01L21/50 ,  B81C1/00 ,  B81C3/00

CPC classification number: H01L23/562 ,  B81C1/00269 ,  B81C1/00357 ,  B81C3/001 ,  B81C2201/019 ,  H01L21/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided.

Abstract translation: 堆叠晶片结构包括基板; 堤坝设置在基板上并在其表面上具有突起; 以及设置在坝上的具有凹槽的晶片。 坝的表面上的突起楔入晶片的凹槽中，防止在晶片的凹槽和坝之间形成空气室，使得晶片由于存在气室而不与坝隔离 随后的包装过程。 还提供了一种堆叠晶片的方法。

公开(公告)号：US20130285215A1

公开(公告)日：2013-10-31

申请号：US13845728

申请日：2013-03-18

Applicant: XINTEC INC.

Inventor： Yu-Lin Yen ,  Hsi-Chien Lin ,  Yeh-Shih Ho

IPC: H01L23/00 ,  H01L21/50

CPC classification number: H01L23/562 ,  B81C1/00269 ,  B81C1/00357 ,  B81C3/001 ,  B81C2201/019 ,  H01L21/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided.

Abstract translation: 堆叠晶片结构包括基板; 堤坝设置在基板上并在其表面上具有突起; 以及设置在坝上的具有凹槽的晶片。 坝的表面上的突起楔入晶片的凹槽中，防止在晶片的凹槽和坝之间形成空气室，使得晶片由于存在气室而不与坝隔离 随后的包装过程。 还提供了一种堆叠晶片的方法。

公开(公告)号：US20130187263A1

公开(公告)日：2013-07-25

申请号：US13738082

申请日：2013-01-10

Applicant: Xintec Inc.

Inventor： Po-Shen Lin ,  Chuan-Jin Shiu ,  Bing-Siang Chen ,  Chen-Han Chiang ,  Chien-Hui Chen ,  Hsi-Chien Lin ,  Yen-Shih Ho

IPC: H01L21/78 ,  H01L23/12

CPC classification number: H01L21/78 ,  B81C1/00888 ,  H01L21/561 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided.

Abstract translation: 提供一种制造半导体堆叠封装的方法。 在晶片和基板上进行单晶化处理，晶片和晶片被堆叠在其上。 去除切割区域上的晶片的一部分，以在晶片的芯片的边缘上形成应力集中区域。 然后切割晶片和基板，并且迫使应力集中在晶片的芯片的边缘上。 结果，芯片的边缘变形。 因此，防止了应力延伸到芯片的内部。 还提供半导体堆叠封装。