公开(公告)号：US09881959B2

公开(公告)日：2018-01-30

申请号：US14819348

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Po-Shen Lin ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687

Abstract: A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A color filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the color filter. The carrier substrate is removed.

公开(公告)号：US09426894B2

公开(公告)日：2016-08-23

申请号：US14282457

申请日：2014-05-20

Applicant: XINTEC INC.

Inventor： Yi-Ming Chang ,  I-Min Lin ,  Po-Shen Lin

IPC: H05K3/06 ,  H01L21/48 ,  H01L21/768 ,  H01L23/532 ,  H05K3/40 ,  H05K3/24 ,  H01L23/00

CPC classification number: H05K3/06 ,  H01L21/4853 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02317 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/00

Abstract: A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.

Abstract translation: 提供了一种用于改善冠状缺陷的布线结构及其制造方法。 该方法包括以下步骤。 提供了其上形成有种子层和具有开口的图案化光致抗蚀剂层的衬底。 在开口中形成有覆盖种子层的底部的铜层。 覆盖铜层的至少一个顶部的阻挡层形成在铜层上。 阻挡层的氧化电位大于铜层的氧化电位。 去除图案化的光致抗蚀剂层以进行蚀刻工艺，其中铜层和暴露的种子层的一部分被蚀刻以形成布线层。 进行浸渍处理以在阻挡层和布线层的暴露表面上综合地形成抗氧化层。

公开(公告)号：US09153528B2

公开(公告)日：2015-10-06

申请号：US13898300

申请日：2013-05-20

Applicant: XINTEC INC.

Inventor： Po-Shen Lin ,  Tsang-Yu Liu ,  Yen-Shih Ho ,  Chih-Wei Ho ,  Yu-Min Liang

IPC: H01L21/78 ,  H01L23/498 ,  H01L23/00 ,  B81B7/00 ,  H01L27/146

CPC classification number: H01L23/498 ,  B81B7/0077 ,  H01L21/78 ,  H01L24/94 ,  H01L27/14618 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer.

Abstract translation: 本发明的实施例提供了一种芯片封装，包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 设置在所述第一表面上的电介质层; 以及导电焊盘结构，其设置在所述电介质层中并且电连接到所述器件区域; 设置在所述芯片和所述盖基板之间的覆盖基板，其中所述间隔层，空腔由所述芯片和所述器件区域上的覆盖基板所围绕，并且所述间隔层与所述芯片直接接触而没有任何粘合胶 设置在芯片和间隔层之间。

公开(公告)号：US20130187263A1

公开(公告)日：2013-07-25

申请号：US13738082

申请日：2013-01-10

Applicant: Xintec Inc.

Inventor： Po-Shen Lin ,  Chuan-Jin Shiu ,  Bing-Siang Chen ,  Chen-Han Chiang ,  Chien-Hui Chen ,  Hsi-Chien Lin ,  Yen-Shih Ho

IPC: H01L21/78 ,  H01L23/12

CPC classification number: H01L21/78 ,  B81C1/00888 ,  H01L21/561 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided.

Abstract translation: 提供一种制造半导体堆叠封装的方法。 在晶片和基板上进行单晶化处理，晶片和晶片被堆叠在其上。 去除切割区域上的晶片的一部分，以在晶片的芯片的边缘上形成应力集中区域。 然后切割晶片和基板，并且迫使应力集中在晶片的芯片的边缘上。 结果，芯片的边缘变形。 因此，防止了应力延伸到芯片的内部。 还提供半导体堆叠封装。