公开(公告)号：US09548265B2

公开(公告)日：2017-01-17

申请号：US15138119

申请日：2016-04-25

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Hsing-Lung Shen ,  Yu-Hao Su ,  Kuan-Jung Wu ,  Yi Cheng

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L21/687 ,  H01L49/02

CPC classification number: H01L23/49838 ,  C25D17/001 ,  C25D17/005 ,  C25D17/06 ,  H01L21/2885 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/68721 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L28/10 ,  H01L2224/11

Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.

Abstract translation: 芯片封装包括芯片，隔离层和再分配层。 芯片具有基板，电焊盘和保护层。 基板具有第一表面和第二表面。 基板具有通孔，保护层具有凹孔，使得电焊盘通过凹孔和通孔露出。 隔离层位于第二表面，通孔的侧壁和凹孔的侧壁上。 再分配层包括连接部分和无源元件部分。 连接部分位于隔离层上并与电焊垫电接触。 无源元件部分位于第二表面上的隔离层上，无源元件部分的一端连接到第二表面上的连接部分。

公开(公告)号：US10446504B2

公开(公告)日：2019-10-15

申请号：US15980577

申请日：2018-05-15

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Po-Han Lee ,  Wei-Chung Yang ,  Kuan-Jung Wu ,  Shu-Ming Chang

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H01L27/146

Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.