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公开(公告)号：US11689207B1
公开(公告)日：2023-06-27
申请号：US17694550
申请日：2022-03-14
Applicant: XILINX, INC.
Inventor： Adebabay M. Bekele , Parag Upadhyaya
CPC classification number: H03L7/099 , H03B5/1253 , H03B5/1296 , H03L7/093
Abstract: Phase-locked loop circuitry generates an output signal based on transformer based voltage controlled oscillator (VCO) circuitry. The VCO circuitry includes upper band circuitry including first oscillation circuitry, a first harmonic filter circuitry coupled to the first oscillation circuitry, and a first selection transistor coupled to the first harmonic filter circuitry and a current source. The first harmonic filter circuitry filters the output signal. The lower band circuitry includes second oscillation circuitry, a second harmonic filter circuitry coupled to the second oscillation circuitry, and a second selection transistor coupled to the second harmonic filter circuitry and the current source. The second harmonic filter circuitry filters the output signal.
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公开(公告)号：US09325277B1
公开(公告)日：2016-04-26
申请号：US14571805
申请日：2014-12-16
Applicant: Xilinx, Inc.
Inventor： Adebabay M. Bekele , Parag Upadhyaya
IPC: H03B5/12
CPC classification number: H03B5/1253 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B5/1271 , H03B5/1278 , H03B5/129 , H03B2201/0208 , H03B2201/0266 , H03B2201/0291 , H03B2201/031 , H03B2201/038
Abstract: Voltage-controlled oscillation is described. In an apparatus therefor, an inductor has a tap and has or is coupled to a positive-side output node and a negative side output node. The tap is coupled to receive a first current. A coarse grain capacitor array is coupled to the positive-side output node and the negative side output node and is coupled to respectively receive select signals. A varactor is coupled to the positive-side output node and the negative side output node and is coupled to receive a control voltage. The varactor includes MuGFETs. A transconductance cell is coupled to the positive-side output node and the negative side output node, and the transconductance cell has a common node. A frequency scaled resistor network is coupled to the common node and is coupled to receive the select signals for a resistance for a path for a second current.
Abstract translation: 描述了压控振荡。 在其装置中，电感器具有抽头并且具有或耦合到正侧输出节点和负侧输出节点。 抽头被耦合以接收第一电流。 粗粒电容器阵列耦合到正侧输出节点和负侧输出节点，并被耦合以分别接收选择信号。 变容二极管耦合到正侧输出节点和负侧输出节点，并耦合以接收控制电压。 变异反应器包括MuGFETs。 跨导单元耦合到正侧输出节点和负侧输出节点，并且跨导单元具有公共节点。 频率比例电阻网络耦合到公共节点，并被耦合以接收用于第二电流的路径的电阻的选择信号。
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Patent Agency Ranking
公开(公告)号：US11637528B1
公开(公告)日：2023-04-25
申请号：US17689748
申请日：2022-03-08
Applicant: XILINX, INC.
Inventor： Adebabay M. Bekele , Parag Upadhyaya
Abstract: Transformer based voltage controlled oscillator circuitry for phase-locked loop circuitry includes upper band circuitry and lower band circuitry. The upper band circuitry operates in a first frequency range and includes a first capacitor array having a variable capacitance. The lower band circuitry operates in a second frequency range and includes a second capacitor array having a variable capacitance. The first frequency range higher than the second frequency range. In a first operating mode, the first capacitor array has a first capacitance value and the second capacitor array has a second capacitance value. In a second operating mode, the second capacitor array has a third capacitance value different than the second capacitance value.
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公开(公告)号：US10715153B1
公开(公告)日：2020-07-14
申请号：US16517103
申请日：2019-07-19
Applicant: XILINX, INC.
Inventor： Adebabay M. Bekele , Parag Upadhyaya , Didem Z. Turker Melek , Jing Jing
Abstract: Apparatus and associated methods relate to automatically generating a data structure representation of an on-chip inductive-capacitive (LC) tank circuit by determining parasitic inductances in each of the segments of conductive paths that connect a main inductor to one or more selectable VCO components such as capacitors and varactors, for example. In an illustrative example, one or more of the selectable VCO components may be arranged, when selected, to form a parallel resonant LC tank with the main inductor. A method may include defining nodes ai terminating each of the segments along the conductive paths between the main inductor terminals and a drive circuit. By modelling the paths as multi-port inductors and transformers, resonant frequency of the VCO may be more accurately predicted by simulation.
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5.发明申请公开(公告)号：US20160322979A1
公开(公告)日：2016-11-03
申请号：US14700695
申请日：2015-04-30
Applicant: Xilinx, Inc.
Inventor： Parag Upadhyaya , Adebabay M. Bekele , Didem Z. Turker Melek , Zhaoyin D. Wu
Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.
Abstract translation: 在一个示例中，锁相环（PLL）电路包括可操作以产生误差信号的误差检测器; 振荡器，其可操作以提供具有基于所述误差信号和频带选择信号的输出频率的输出信号，所述输出频率是频率乘数乘以参考频率; 分频器，用于将输出信号的输出频率除以基于分频器控制信号产生反馈信号; Σ-Δ调制器（SDM），可操作以基于表示所述倍频器的整数值和分数值的输入产生所述除法器控制信号，所述SDM响应于可操作以选择所述SDM的次序的订单选择信号; 以及状态机，其可操作以在获取状态下生成所述频带选择信号并设置所述SDM的顺序。
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公开(公告)号：US09742380B1
公开(公告)日：2017-08-22
申请号：US15170797
申请日：2016-06-01
Applicant: Xilinx, Inc.
Inventor： Mayank Raj , Parag Upadhyaya , Adebabay M. Bekele
IPC: H03L7/06 , H03K3/013 , H03K5/04 , H03K7/08 , H03L7/18 , H03L7/197 , H03L7/093 , H03L7/091 , H03L7/089
CPC classification number: H03K3/013 , H03K5/04 , H03K7/08 , H03L7/0891 , H03L7/0895 , H03L7/0898 , H03L7/091 , H03L7/093 , H03L7/18 , H03L7/1974
Abstract: An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider configured to generate the reference clock from the output clock.
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公开(公告)号：US09608644B1
公开(公告)日：2017-03-28
申请号：US15172442
申请日：2016-06-03
Applicant: Xilinx, Inc.
Inventor： Mayank Raj , Parag Upadhyaya , Adebabay M. Bekele
CPC classification number: H03L7/087 , H03L7/081 , H03L7/0895 , H03L7/091 , H03L7/095 , H03L7/1075 , H03L7/113
Abstract: An example phase-locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) configured to generate an output clock based on an oscillator control voltage, a sub-sampling phase detector configured to receive a reference clock and the output clock, and a phase frequency detector configured to receive the reference clock and a feedback clock. The PLL circuit includes a charge pump configured to generate a charge pump current, a multiplexer circuit configured to select either output of the sub-sampling phase detector or output of the phase frequency detector to control the charge pump, and a lock detector configured to receive the reference clock, the feedback clock, and the output of the phase frequency detector to control the multiplexer. The PLL circuit includes a loop filter configured to filter the charge pump current and generate the oscillator control voltage, and a frequency divider configured to generate the reference clock from the output clock.
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