公开(公告)号：US11730325B2

公开(公告)日：2023-08-22

申请号：US17468346

申请日：2021-09-07

Applicant: XILINX, INC.

Inventor： Peter McColgan ,  Goran Hk Bilski ,  Juan J. Noguera Serra ,  Jan Langer ,  Baris Ozgul ,  David Clarke

IPC: G06F21/85 ,  A47K11/02 ,  E04H1/12 ,  E04H15/38 ,  G06F13/40

CPC classification number: A47K11/02 ,  E04H1/1216 ,  E04H15/38 ,  G06F13/4022 ,  Y02A50/30

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.

公开(公告)号：US11853235B2

公开(公告)日：2023-12-26

申请号：US17826068

申请日：2022-05-26

Applicant: XILINX, INC.

Inventor： Juan J. Noguera Serra ,  Goran Hk Bilski ,  Baris Ozgul ,  Jan Langer

IPC: G06F13/16 ,  G06F12/084 ,  G06F9/54 ,  G11C8/16 ,  G06F15/167

CPC classification number: G06F13/1663 ,  G06F9/544 ,  G06F12/084 ,  G06F15/167 ,  G11C8/16

Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

公开(公告)号：US11669464B1

公开(公告)日：2023-06-06

申请号：US16858417

申请日：2020-04-24

Applicant: XILINX, INC.

Inventor： Goran Hk Bilski ,  Baris Ozgul ,  David Clarke ,  Juan J. Noguera Serra ,  Jan Langer ,  Zachary Dickman ,  Sneha Bhalchandra Date ,  Tim Tuan

IPC: G06F12/1081 ,  G06F12/06 ,  G06F9/52 ,  G06F15/78 ,  G06F12/02

CPC classification number: G06F12/1081 ,  G06F9/524 ,  G06F12/0246 ,  G06F12/0607 ,  G06F15/7807

Abstract: Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.

公开(公告)号：US11386020B1

公开(公告)日：2022-07-12

申请号：US16808054

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Matthew H. Klein ,  Goran Hk Bilski ,  Juan Jose Noguera Serra ,  Ismed D. Hartanto ,  Sridhar Subramanian ,  Tim Tuan

IPC: G06F15/17 ,  G06F13/16 ,  G06F9/30 ,  H03K19/1776 ,  G06F7/501 ,  G06F15/173

Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.

公开(公告)号：US11599498B1

公开(公告)日：2023-03-07

申请号：US17068697

申请日：2020-10-12

Applicant: XILINX, INC.

Inventor： Juan J. Noguera Serra ,  Sneha Bhalchandra Date ,  Jan Langer ,  Baris Ozgul ,  Goran Hk Bilski

IPC: G06F9/00 ,  G06F15/177 ,  G06F15/80 ,  G06F15/173 ,  G06F9/4401

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US11323391B1

公开(公告)日：2022-05-03

申请号：US16833029

申请日：2020-03-27

Applicant: XILINX, INC.

Inventor： Peter McColgan ,  David Clarke ,  Goran Hk Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Tim Tuan

IPC: H04L12/935 ,  G06F13/28 ,  H04L49/00

Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.

公开(公告)号：US10990552B1

公开(公告)日：2021-04-27

申请号：US15944464

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran Hk Bilski ,  Peter McColgan ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/40 ,  G06F13/42

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.