公开(公告)号：US09405871B1

公开(公告)日：2016-08-02

申请号：US14562359

申请日：2014-12-05

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Vinod K. Nakkala ,  Atul Srinivasan ,  Sudip K. Nag

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081

Abstract: Determining delays of paths in a circuit design includes determining whether or not each path of the plurality of paths matches a path definition of a plurality of path definitions in a path database. For each path that matches a path definition, a first path delay value associated with the matching path definition is read from the path database and associated with the matching path of the circuit design. For each path that does not match any of the path definitions, respective element delay values of elements of the path are read from an element database. A second path delay value of the non-matching path is computed as a function of the respective element delay values, and the second path delay value is associated with the path. The first and second path delay values are output along with information indicating the associated paths.

Abstract translation: 确定电路设计中的路径的延迟包括确定多个路径中的每个路径是否与路径数据库中的多个路径定义的路径定义相匹配。 对于与路径定义匹配的每个路径，从路径数据库读取与匹配路径定义相关联的第一路径延迟值，并与电路设计的匹配路径相关联。 对于不匹配任何路径定义的每个路径，从元素数据库读取路径元素的相应元素延迟值。 根据相应的元件延迟值计算非匹配路径的第二路径延迟值，并且第二路径延迟值与路径相关联。 第一和第二路径延迟值与指示相关联的路径的信息一起被输出。

公开(公告)号：US09885750B1

公开(公告)日：2018-02-06

申请号：US14750049

申请日：2015-06-25

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri

IPC: G06F17/50 ,  G01R31/317 ,  H03K19/177

CPC classification number: G01R31/31718 ,  G01R31/31725 ,  H03K19/17748

Abstract: Techniques for intelligent tuning of speed models for configurable integrated circuits. The techniques consider data related to yield, quality-of-results, and data for individual programmable-interconnect-point (PIP)-contexts. More specifically, the speed of yield-related structures, quality-of-results related structures, and structures for measuring individual PIP-contexts are measured. These measurements are compared with estimated values stored as part of a speed model and scaling factors for the stored estimated values are calculated. The scaling factors are applied to the estimated values within the speed model and measurements are repeated if desired.

公开(公告)号：US09372948B1

公开(公告)日：2016-06-21

申请号：US14730609

申请日：2015-06-04

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri

IPC: H03K19/00 ,  G06F17/50 ,  G01R31/317 ,  G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318594 ,  G01R31/2834 ,  G01R31/31725 ,  G06F17/5036 ,  G06F2217/84

Abstract: Techniques for using a speed measurement circuit to measure speed of an integrated circuit. The speed measurement circuit includes a ring oscillator and a counter circuit. The ring oscillator includes an AND gate with an inverting input and a non-inverting input. The ring oscillator also includes a programmable interconnect point context (PIP-context) having a first programmable interconnect point (PIP), a first interconnect, a second PIP, and a second interconnect coupled in series. The ring oscillator also includes a third interconnect and a third PIP coupled in series with the PIP-context and with an inverting input of the AND gate. The counter circuit is coupled to an output of the AND gate and configured in the programmable integrated circuit.

Abstract translation: 使用速度测量电路测量集成电路速度的技术。 速度测量电路包括环形振荡器和计数器电路。 环形振荡器包括具有反相输入和非反相输入的与门。 环形振荡器还包括具有串联耦合的第一可编程互连点（PIP），第一互连，第二PIP和第二互连的可编程互连点上下文（PIP上下文）。 环形振荡器还包括与PIP上下文串联耦合的第三互连和第三PIP以及与门的反相输入。 计数器电路耦合到与门的输出并配置在可编程集成电路中。

公开(公告)号：US09639640B1

公开(公告)日：2017-05-02

申请号：US14693506

申请日：2015-04-22

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Robert M. Ondris ,  Chiao K. Hwang

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5027 ,  G06F17/5054 ,  G06F2217/62 ,  G06F2217/84

Abstract: An approach for generating delay values for circuit elements in a clock network of a programmable IC includes determining for each clock resource in the clock network, different possible contexts of the clock resource. Each context specifies a combination of possible types of circuit elements in the context. Circuit elements of the possible types are selected from the different contexts, and configuration data is generated for implementation of respective ring oscillator circuits that include the selected circuit elements. The programmable IC is configured with the configuration data, and the programmable IC as configured with the respective ring oscillator circuits is operated. Respective delay values of the selected circuit elements are determined from output of the ring oscillator circuits. The delay values are stored in association with identifiers of the selected circuit elements in a memory arrangement.

公开(公告)号：US09501604B1

公开(公告)日：2016-11-22

申请号：US14493750

申请日：2014-09-23

Applicant: Xilinx, Inc.

Inventor： Geetesh More ,  Srinivasan Dasasathyan ,  Nagaraj Savithri

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5027 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

Abstract: A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.

Abstract translation: 一种测试电路设计的方法包括为电路设计中的每个关键路径的每个网络产生相应的环形振荡器电路设计。 环形振荡器电路设计具有经由网络耦合到目的地门的源极和将目的地门的输出引脚耦合到源极栅极的输入引脚的反馈路径。 生成配置数据以实现来自每个环形振荡器电路设计的相应环形振荡器电路，并且可编程集成电路被配置有配置数据。 该方法确定每个环形振荡器电路的网络的延迟。

公开(公告)号：US10289784B1

公开(公告)日：2019-05-14

申请号：US15432537

申请日：2017-02-14

Applicant: Xilinx, Inc.

Inventor： Chiao K. Hwang ,  Zicheng G. Ling ,  Nagaraj Savithri

IPC: G06F17/50

Abstract: The disclosed approaches process a circuit design that specifies a clock signal. A plurality of wire segments of an integrated circuit (IC) are selected for a clock path to carry the clock signal. A delay of the clock path is determined based on delay values associated with identifiers of the wire segments and variation factors. Configuration data is generated from the circuit design once the delay of the clock path satisfies a timing constraint, and a circuit is generated from the configuration data to implement a circuit according to the circuit design.

公开(公告)号：US10162916B1

公开(公告)日：2018-12-25

申请号：US15433766

申请日：2017-02-15

Applicant: Xilinx, Inc.

Inventor： Usha Narasimha ,  Atul Srinivasan ,  Nagaraj Savithri

IPC: G06F17/50 ,  G06F17/11

Abstract: Disclosed approaches for processing a circuit design targeted to a programmable integrated circuit (IC) include inputting the circuit design to a programmed processor. Each path of the circuit design specifies a plurality of circuit elements of the programmable IC. For each circuit element specified in a path of the plurality of paths the processor looks up in a memory a mean delay associated with the circuit element, looks up a sigma factor associated with the circuit element, and looks up a delta factor associated with the circuit element. The processor determines a delay of the path as a function of the mean delay, sigma factor, and delta factor of each circuit element in the path.

公开(公告)号：US09915696B1

公开(公告)日：2018-03-13

申请号：US14792189

申请日：2015-07-06

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Fu-Hing Ho

IPC: G06F19/00 ,  G01R31/36 ,  G01R31/317 ,  G01R31/28 ,  G01R31/3183

CPC classification number: G01R31/3016 ,  G01R31/31725 ,  G01R31/318516

Abstract: Techniques for adaptively scaling power supply voltage of a programmable integrated circuit. Compact speed-testing ring oscillators are inserted into a pre-constructed circuit model to test the speed of speed-critical aspects of the interconnect fabric of the programmable integrated circuit. The speed-testing ring oscillators are compact due to including only two elements configured from lookup table elements (“LUTs”) of the programmable integrated circuit. The speed-testing ring oscillators are connected to a power management unit which receives speed values output from the speed-testing ring oscillators and adjusts the power supply voltage to maintain the speed-testing ring oscillators operating at or above a prescribed speed. If all speed-testing ring oscillators are operating too fast, then power management unit reduces voltage to reduce the total power consumed by the programmable integrated circuit while still maintaining operation above a desired speed.

公开(公告)号：US09065446B1

公开(公告)日：2015-06-23

申请号：US14294406

申请日：2014-06-03

Applicant: Xilinx, Inc.

Inventor： Nagaraj Savithri ,  Amit Gupta ,  Fu-Hing Ho

IPC: G06F17/50 ,  H03K19/177

CPC classification number: H03K19/17792 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5054 ,  G06F2217/84 ,  H03K19/1774

Abstract: Approaches for generating delay values for instances of a circuit include inputting possible contexts of the circuit. Each context includes a respective delay value and a combination of possible types of a plurality of characteristics of the circuit, and each characteristic is of one type of a plurality of alternative types of the characteristic. A plurality of classification parameters is input and the classification parameters indicate selected ones of the characteristics. Groups of contexts are selected based on the plurality of classification parameters. Each group includes one or more of the contexts, and each context includes the plurality of characteristics. A combination of types of the selected characteristics in each context in a group is equal to the combination of types of the selected characteristics of each other context in the group. For each group, a mean and a standard deviation of the respective delay values are determined and output.

Abstract translation: 为电路实例产生延迟值的方法包括输入电路的可能上下文。 每个上下文包括各自的延迟值和电路的多个特性的可能类型的组合，并且每个特征是特征的多种替代类型的一种类型。 输入多个分类参数，分类参数表示选定的特征。 基于多个分类参数来选择上下文组。 每个组包括上下文中的一个或多个，并且每个上下文包括多个特征。 组中每个上下文中所选特征的类型的组合等于组中每个其他上下文的所选特征的类型的组合。 对于每个组，确定并输出各个延迟值的平均值和标准偏差。