公开(公告)号：US20130043537A1

公开(公告)日：2013-02-21

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

公开(公告)号：US08963246B2

公开(公告)日：2015-02-24

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/144 ,  H01L29/861 ,  H01L29/786

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Abstract translation: 提供了半导体器件和半导体器件的制造方法。 在由高电阻N型衬底形成的N型半导体层内，形成P型阱扩散层和P型提取层，并将其固定为接地电位。 由此，在P型阱扩散层侧扩散的耗尽层未达到P型阱扩散层与埋入氧化膜之间的层间界限。 因此，P型阱扩散层的表面周围的电位保持在接地电位。 因此，当将电压施加到N型半导体层和阴极的背面时，形成为P型半导体层的MOS型半导体的沟道区域不被激活。 由此，能够抑制由于晶体管的栅电极引起的控制而发生的漏电流。

公开(公告)号：US08928101B2

公开(公告)日：2015-01-06

申请号：US13253791

申请日：2011-10-05

Applicant: Hiroki Kasai ,  Yasuo Arai ,  Takaki Hatsui

Inventor： Hiroki Kasai ,  Yasuo Arai ,  Takaki Hatsui

IPC: H01L31/0224 ,  H01L27/146 ,  H01L27/12

CPC classification number: H01L27/14607 ,  H01L27/1203 ,  H01L27/14659

Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; an insulation layer on the first semiconductor layer; a second semiconductor layer in the insulation layer; an active element in the second semiconductor layer; a first semiconductor region on the first semiconductor layer and of a second conductivity type; a second semiconductor region in the first semiconductor region and of the second conductivity type with a higher impurity concentration than the first semiconductor region; a first conductor in a through hole in the insulation layer and connected to the second semiconductor region; a second conductor above or within the insulation layer, the second conductor surrounding the first conductor such that an outside edge thereof is outside the second semiconductor region; a third conductor connecting the first and second conductors; and a fourth conductor connected to the first semiconductor layer.

Abstract translation: 半导体器件包括：第一导电类型的第一半导体层; 第一半导体层上的绝缘层; 绝缘层中的第二半导体层; 第二半导体层中的有源元件; 第一半导体区域和第二导电类型的第一半导体区域; 在第一半导体区域中的第二半导体区域和具有比第一半导体区域更高的杂质浓度的第二导电类型的第二半导体区域; 绝缘层中的通孔中的第一导体，并连接到第二半导体区; 绝缘层之上或之内的第二导体，所述第二导体围绕所述第一导体，使得其外边缘在所述第二半导体区域的外部; 连接第一和第二导体的第三导体; 以及连接到第一半导体层的第四导体。

公开(公告)号：US20100237413A1

公开(公告)日：2010-09-23

申请号：US12659161

申请日：2010-02-26

Applicant: Hiroki Kasai

Inventor： Hiroki Kasai

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0657 ,  H01L21/26586 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7816

Abstract: A semiconductor device has a LOCOS film formed on at least one of a drain side and a source side of a semiconductor substrate surface. A gate oxide film connected to the LOCOS film is formed on the semiconductor substrate surface. A conductive film is formed to cover the gate oxide film and the LOCOS film. A gate electrode is formed by etching the conductive film such that an end portion of the conductive film is positioned above the LOCOS film. The LOCOS film is etched such that an end portion of the LOCOS film is in alignment with an end portion of the gate electrode, thereby forming a recessed portion in a part of the semiconductor substrate surface from which the LOCOS film has been removed. A side wall spacer is formed to cover a side surface of the gate electrode such that a bottom surface of the side wall spacer contacts a surface of the recessed portion. A drain region and a source region are formed by doping a impurity to the semiconductor substrate surface on either side of the gate electrode and the side wall spacer.

Abstract translation: 半导体器件具有形成在半导体衬底表面的漏极侧和源极侧的至少一个上的LOCOS膜。 连接到LOCOS膜的栅极氧化膜形成在半导体衬底表面上。 形成导电膜以覆盖栅氧化膜和LOCOS膜。 通过蚀刻导电膜使得导电膜的端部位于LOCOS膜上方形成栅电极。 蚀刻LOCOS膜，使得LOCOS膜的端部与栅电极的端部对准，从而在已经去除了LOCOS膜的半导体衬底表面的一部分中形成凹陷部分。 形成侧壁隔离物以覆盖栅电极的侧表面，使得侧壁间隔件的底表面与凹部的表面接触。 通过将杂质掺杂到栅电极和侧壁间隔物的任一侧上的半导体衬底表面来形成漏极区和源极区。