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    HDP gap-filling process for structures with extra step at side-wall
    1.
    发明授权
    HDP gap-filling process for structures with extra step at side-wall 失效
    HDP间隙填充过程，用于侧壁额外加工的结构

    公开(公告)号：US06780731B1

    公开(公告)日：2004-08-24

    申请号：US10225803

    申请日：2002-08-22

    申请人： Yeur-Luen Tu ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Yuan-Hung Liu

    发明人： Yeur-Luen Tu ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Yuan-Hung Liu

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang. This approach is found to prevent the formation of an overhang at the position of the step, whereat it would cause progressive restriction of the trench throat and void formation.

    摘要翻译： 一种多步骤HDP沉积和溅射方法，用于无缝填充具有阶梯形横截面轮廓的高纵横比沟槽。 该方法特别适用于填充形成在包括硅第一层，氧化物第二层和氮化物第三层的三层分层衬底中的沟槽，其中氮化物层从沟槽开口的边缘被拉回并形成一个台阶。 该方法允许这种沟槽的无空隙填充，而不会使该过程中的氮化物层老化。 简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比沉积，并且具有低偏压能力以在上表面形成具有突出端的层 沟。 该沉积如果随后是溅射工艺以在该突出端形成扩大的开口。 发现这种方法可以防止在台阶位置形成突出端，从而导致沟槽喉部和空隙形成的逐渐限制。

    Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence
    2.
    发明授权
    Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence 失效
    在外径（OD）和强栅栏上制作用于宽过度蚀刻窗口的字线间隔件的方法

    公开(公告)号：US06869837B1

    公开(公告)日：2005-03-22

    申请号：US10758316

    申请日：2004-01-15

    申请人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

    发明人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

    IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.

    摘要翻译： 一种制造字线间隔物的方法，包括以下步骤。 提供了具有形成在其上的初始分离栅闪存结构的衬底。 导电层形成在衬底和初生分裂栅极闪存结构之上。 所述导电层具有：上部分裂栅极闪存结构上方的上部和下部垂直部分; 并且在基底上下方水平部分。 在导电层之上形成双层氧化物层，并且在导电层的上部上具有更大的厚度。 将氧化层部分地回蚀刻以从导电层的下部水平部分上方至少去除氧化物层，以暴露导电层的下面部分。 然后蚀刻：将导电层的暴露部分远离衬底; 并且通过至少一部分减薄的氧化物层并进入导电层的暴露的下面的部分，以暴露初步分离栅闪存结构的一部分并且形成邻近先驱分离栅闪存的字线间隔物 结构体。

    Method of forming MIM capacitor electrodes
    3.
    发明申请
    Method of forming MIM capacitor electrodes 有权
    形成MIM电容器电极的方法

    公开(公告)号：US20050215004A1

    公开(公告)日：2005-09-29

    申请号：US10811657

    申请日：2004-03-29

    申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    IPC分类号： H01G4/005 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L23/522 ,  H01L29/06

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

    摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

    Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches
    4.
    发明授权
    Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches 有权
    薄侧壁多步骤HDP沉积方法实现完全填充的高纵横比沟槽

    公开(公告)号：US06653203B1

    公开(公告)日：2003-11-25

    申请号：US10154285

    申请日：2002-05-23

    申请人： Tsung-Hsun Huang ,  Yeur-Luen Tu ,  Chung Yi Yu

    发明人： Tsung-Hsun Huang ,  Yeur-Luen Tu ,  Chung Yi Yu

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224 ,  H01L21/76232

    摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches and for trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon layer, an oxide layer and a nitride layer, wherein the nitride layer has been pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without damaging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the sidewalls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio (D/S>10) and low bias power to form a thin layer, with no overhang, that is capable of protecting the nitride layer during subsequent deposition and sputtering steps. A subsequent in-situ sputtering step at a lower D/S ratio using oxygen as the sputtering gas maintains a wide trench opening which then allows the complete filling to proceed using argon as the sputtering gas for increased throughput.

    摘要翻译： 用于无高度填充高纵横比沟槽和具有阶梯形截面轮廓的沟槽的多步HDP沉积和溅射工艺。 该方法特别适用于填充形成在包括硅层，氧化物层和氮化物层的三层分层衬底中的沟槽，其中氮化物层已从沟槽开口的边缘拉回并形成一个步骤。 该方法允许这种沟槽的无空隙填充而不损害该过程中的氮化物层。 简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比（D / S> 10）沉积并具有低偏压功率以形成薄层，其中 没有悬垂，在后续沉积和溅射步骤中能够保护氮化物层。 使用氧作为溅射气体的较低D / S比率的随后的原位溅射步骤保持宽的沟槽开口，然后允许使用氩气作为溅射气体进行完全填充以提高生产量。

    Method of forming MIM capacitor electrodes
    5.
    发明授权
    Method of forming MIM capacitor electrodes 有权
    形成MIM电容器电极的方法

    公开(公告)号：US07199001B2

    公开(公告)日：2007-04-03

    申请号：US10811657

    申请日：2004-03-29

    申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

    摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

    Method for reducing leakage current in a semiconductor device
    6.
    发明申请
    Method for reducing leakage current in a semiconductor device 有权
    减少半导体器件漏电流的方法

    公开(公告)号：US20060278959A1

    公开(公告)日：2006-12-14

    申请号：US11149575

    申请日：2005-06-10

    申请人： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

    发明人： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

    IPC分类号： H01L23/58 ,  H01L21/38

    CPC分类号： H01L21/76829 ,  H01L21/3003 ,  H01L21/3105 ,  H01L21/3143 ,  H01L21/76828

    摘要： A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.

    摘要翻译： 公开了一种用于减小半导体结构中的漏电流的方法。 一个或多个电介质层形成在半导体衬底上，其上构造有至少一个器件。 在电介质层上形成含氢层。 氮化硅钝化层覆盖电介质层和含氢层。 含氢层的氢原子被引入到电介质层中而不被氮化硅层阻挡，从而减少其中的漏电流。

    Semiconductor device having hydrogen-containing layer
    8.
    发明授权
    Semiconductor device having hydrogen-containing layer 有权
    具有含氢层的半导体装置

    公开(公告)号：US07786552B2

    公开(公告)日：2010-08-31

    申请号：US11149575

    申请日：2005-06-10

    申请人： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

    发明人： Tsung-Hsun Huang ,  Kuo-Yin Lin ,  Chung-Yi Yu ,  Chih-Ta Wu ,  Chia-Shiung Tsai

    IPC分类号： H01L23/58

    CPC分类号： H01L21/76829 ,  H01L21/3003 ,  H01L21/3105 ,  H01L21/3143 ,  H01L21/76828

    摘要： A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A silicon nitride passivation layer covers the dielectric layers and the hydrogen-containing layer. The hydrogen atoms of the hydrogen-containing layer are introduced into the dielectric layers without being blocked by the silicon nitride layer, thereby reducing leakage current therein.

    摘要翻译： 公开了一种用于减小半导体结构中的漏电流的方法。 一个或多个电介质层形成在半导体衬底上，其上构造有至少一个器件。 在电介质层上形成含氢层。 氮化硅钝化层覆盖电介质层和含氢层。 含氢层的氢原子被引入到电介质层中而不被氮化硅层阻挡，从而减少其中的漏电流。

    Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor
    10.
    发明授权
    Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor 有权
    自对准金属电极消除金属绝缘子半导体（MIS）电容器的自然氧化效应

    公开(公告)号：US07180116B2

    公开(公告)日：2007-02-20

    申请号：US10861148

    申请日：2004-06-04

    申请人： Min-Hsiung Chiang ,  Chih-Ta Wu ,  Tsung-Hsun Huang

    发明人： Min-Hsiung Chiang ,  Chih-Ta Wu ,  Tsung-Hsun Huang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/0629 ,  H01L27/1085 ,  H01L27/10867 ,  H01L29/6659

    摘要： A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.

    摘要翻译： 一种形成电容器的方法，包括以下步骤。 在电容器区域中的衬底上形成初始电容器，由此衬底的一部分使得初始电容器与隔离浅沟槽隔离（STI）结构分离。 性传播感染 在结构上形成第一介电层。 将第一电介质层图案化为：形成遮蔽复合电容器的部分; 并且暴露STI和至少部分将初步电容器与浅沟槽隔离结构分开的衬底部分。 金属部分至少形成在衬底部分上。 在图案化的第一介电层部分，金属部分和STI上形成第二电介质层，由此至少在衬底部分上形成的金属部分防止在至少衬底部分上形成自然氧化物。 本发明还包括由此形成的结构。