公开(公告)号：US06780731B1

公开(公告)日：2004-08-24

申请号：US10225803

申请日：2002-08-22

申请人： Yeur-Luen Tu ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Yuan-Hung Liu

发明人： Yeur-Luen Tu ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Yuan-Hung Liu

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang. This approach is found to prevent the formation of an overhang at the position of the step, whereat it would cause progressive restriction of the trench throat and void formation.

摘要翻译： 一种多步骤HDP沉积和溅射方法，用于无缝填充具有阶梯形横截面轮廓的高纵横比沟槽。 该方法特别适用于填充形成在包括硅第一层，氧化物第二层和氮化物第三层的三层分层衬底中的沟槽，其中氮化物层从沟槽开口的边缘被拉回并形成一个台阶。 该方法允许这种沟槽的无空隙填充，而不会使该过程中的氮化物层老化。 简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比沉积，并且具有低偏压能力以在上表面形成具有突出端的层 沟。 该沉积如果随后是溅射工艺以在该突出端形成扩大的开口。 发现这种方法可以防止在台阶位置形成突出端，从而导致沟槽喉部和空隙形成的逐渐限制。

公开(公告)号：US06869837B1

公开(公告)日：2005-03-22

申请号：US10758316

申请日：2004-01-15

申请人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.

摘要翻译： 一种制造字线间隔物的方法，包括以下步骤。 提供了具有形成在其上的初始分离栅闪存结构的衬底。 导电层形成在衬底和初生分裂栅极闪存结构之上。 所述导电层具有：上部分裂栅极闪存结构上方的上部和下部垂直部分; 并且在基底上下方水平部分。 在导电层之上形成双层氧化物层，并且在导电层的上部上具有更大的厚度。 将氧化层部分地回蚀刻以从导电层的下部水平部分上方至少去除氧化物层，以暴露导电层的下面部分。 然后蚀刻：将导电层的暴露部分远离衬底; 并且通过至少一部分减薄的氧化物层并进入导电层的暴露的下面的部分，以暴露初步分离栅闪存结构的一部分并且形成邻近先驱分离栅闪存的字线间隔物 结构体。

公开(公告)号：US06653203B1

公开(公告)日：2003-11-25

申请号：US10154285

申请日：2002-05-23

申请人： Tsung-Hsun Huang ,  Yeur-Luen Tu ,  Chung Yi Yu

发明人： Tsung-Hsun Huang ,  Yeur-Luen Tu ,  Chung Yi Yu

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches and for trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon layer, an oxide layer and a nitride layer, wherein the nitride layer has been pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without damaging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the sidewalls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio (D/S>10) and low bias power to form a thin layer, with no overhang, that is capable of protecting the nitride layer during subsequent deposition and sputtering steps. A subsequent in-situ sputtering step at a lower D/S ratio using oxygen as the sputtering gas maintains a wide trench opening which then allows the complete filling to proceed using argon as the sputtering gas for increased throughput.

摘要翻译： 用于无高度填充高纵横比沟槽和具有阶梯形截面轮廓的沟槽的多步HDP沉积和溅射工艺。 该方法特别适用于填充形成在包括硅层，氧化物层和氮化物层的三层分层衬底中的沟槽，其中氮化物层已从沟槽开口的边缘拉回并形成一个步骤。 该方法允许这种沟槽的无空隙填充而不损害该过程中的氮化物层。 简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比（D / S> 10）沉积并具有低偏压功率以形成薄层，其中 没有悬垂，在后续沉积和溅射步骤中能够保护氮化物层。 使用氧作为溅射气体的较低D / S比率的随后的原位溅射步骤保持宽的沟槽开口，然后允许使用氩气作为溅射气体进行完全填充以提高生产量。

公开(公告)号：US20050215004A1

公开(公告)日：2005-09-29

申请号：US10811657

申请日：2004-03-29

申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

IPC分类号： H01G4/005 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L23/522 ,  H01L29/06

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

公开(公告)号：US07199001B2

公开(公告)日：2007-04-03

申请号：US10811657

申请日：2004-03-29

申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

公开(公告)号：US20080217775A1

公开(公告)日：2008-09-11

申请号：US11714770

申请日：2007-03-07

申请人： Chih-Yang Pai ,  Wen-Chuan Chiang ,  Chung-Yi Yu ,  Yeur-Luen Tu ,  Yuan-Hung Liu ,  Hsiang-Fan Lee ,  Chuan-Jong Wang

发明人： Chih-Yang Pai ,  Wen-Chuan Chiang ,  Chung-Yi Yu ,  Yeur-Luen Tu ,  Yuan-Hung Liu ,  Hsiang-Fan Lee ,  Chuan-Jong Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/76849 ,  H01L27/10855 ,  H01L27/10888

摘要： A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole.

摘要翻译： 形成eDRAM器件的接触插塞的方法包括以下步骤：在电介质层上形成具有钨接缝的钨层以填充接触孔; 从电介质层的顶表面去除钨层，使接触孔中的钨层凹陷，以在电介质层的顶表面下方深度形成约600〜900埃的凹陷，在电介质层上沉积导电层 和凹入的钨塞填充凹槽; 并且从电介质层的顶表面去除导电层，以在接触孔中的凹入的钨插塞上形成导电插塞。

公开(公告)号：US07824998B2

公开(公告)日：2010-11-02

申请号：US12357661

申请日：2009-01-22

申请人： Yuan-Hung Liu ,  Ming Chyi Liu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Ming Chyi Liu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/20

CPC分类号： H01L21/02274 ,  H01L21/02115 ,  H01L21/28273 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/14632 ,  H01L27/14687 ,  H01L28/91 ,  H01L29/42328 ,  H01L29/7881

摘要： A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.

摘要翻译： 一种方法包括在形成在衬底上的第一电介质层上形成无定形碳层，在非晶碳层上形成第二电介质层; 以及通过第一蚀刻工艺在所述非晶碳层和所述第二介电层内形成开口，以部分地暴露所述第一介电层的顶表面。 在第二电介质层上并在开口内形成基本上共形的含金属层。 去除第二电介质层和一部分含金属层。 通过含氧等离子体工艺除去无定形碳层以暴露第一介电层的顶表面。 在含金属层的上方形成有绝缘层，在绝缘层上形成第二含金属层，形成电容器。

公开(公告)号：US20090130814A1

公开(公告)日：2009-05-21

申请号：US12357661

申请日：2009-01-22

申请人： Yuan-Hung LIU ,  Ming Chyi Liu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chai-Shiung Tsai

发明人： Yuan-Hung LIU ,  Ming Chyi Liu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chai-Shiung Tsai

IPC分类号： H01L21/20

CPC分类号： H01L21/02274 ,  H01L21/02115 ,  H01L21/28273 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/14632 ,  H01L27/14687 ,  H01L28/91 ,  H01L29/42328 ,  H01L29/7881

摘要： A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.

摘要翻译： 一种方法包括在形成在衬底上的第一电介质层上形成无定形碳层，在非晶碳层上形成第二电介质层; 以及通过第一蚀刻工艺在所述非晶碳层和所述第二介电层内形成开口，以部分地暴露所述第一介电层的顶表面。 在第二电介质层上并在开口内形成基本上共形的含金属层。 去除第二电介质层和一部分含金属层。 通过含氧等离子体工艺除去无定形碳层以暴露第一介电层的顶表面。 在含金属层的上方形成有绝缘层，在绝缘层上形成第二含金属层，形成电容器。

公开(公告)号：US08889507B2

公开(公告)日：2014-11-18

申请号：US11765971

申请日：2007-06-20

申请人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

发明人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L49/02 ,  H01L27/108

CPC分类号： H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

摘要翻译： 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

公开(公告)号：US20070096230A1

公开(公告)日：2007-05-03

申请号：US11610760

申请日：2006-12-14

申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

IPC分类号： H01L43/00 ,  H01L29/82

CPC分类号： H01L43/12 ,  H01L27/228

摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。