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    Semiconductor device having an MIS transistor
    1.
    发明授权
    Semiconductor device having an MIS transistor 失效
    具有MIS晶体管的半导体器件

    公开(公告)号：US06774441B2

    公开(公告)日：2004-08-10

    申请号：US10340731

    申请日：2003-01-13

    申请人： Yukio Maki ,  Yoshiyuki Ishigaki ,  Yasuhiro Fujii

    发明人： Yukio Maki ,  Yoshiyuki Ishigaki ,  Yasuhiro Fujii

    IPC分类号： H01L2978

    CPC分类号： H01L29/665 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/6656

    摘要： A semiconductor device according to the present invention includes a silicon substrate having a main surface, a gate electrode provided on the main surface of the silicon substrate, a first sidewall insulating film provided to cover a side surface of the gate electrode and including two layers of an oxide sidewall film as an underlay and a nitride sidewall film, a second sidewall insulating film provided to cover a surface of the first sidewall insulating film, and a cobalt silicide layer arranged above source and drain regions and at a position farther than the second sidewall insulating film from the gate electrode. The second sidewall insulating film fills in a removed portion located at a lower end of the oxide sidewall film. This allows a semiconductor device formed by employing a salicide process to prevent increase of leak current caused by a metal silicide layer.

    摘要翻译： 根据本发明的半导体器件包括具有主表面的硅衬底，设置在硅衬底的主表面上的栅电极，设置成覆盖栅电极的侧表面的第一侧壁绝缘膜，并且包括两层 作为底层的氧化物侧壁膜和氮化物侧壁膜，设置成覆盖第一侧壁绝缘膜的表面的第二侧壁绝缘膜和布置在源极和漏极区之上以及比第二侧壁更远的位置的钴硅化物层 绝缘膜与栅极电极。 第二侧壁绝缘膜填充位于氧化物侧壁膜的下端的去除部分。 这允许通过采用自对准硅化物工艺形成的半导体器件来防止由金属硅化物层引起的漏电流的增加。

    Semiconductor memory device having a latch circuit and storage capacitor
    3.
    发明授权
    Semiconductor memory device having a latch circuit and storage capacitor 有权
    具有锁存电路和存储电容器的半导体存储器件

    公开(公告)号：US06831852B2

    公开(公告)日：2004-12-14

    申请号：US10442439

    申请日：2003-05-22

    申请人： Yoshiyuki Ishigaki ,  Tsuyoshi Koga ,  Yasuhiro Fujii

    发明人： Yoshiyuki Ishigaki ,  Tsuyoshi Koga ,  Yasuhiro Fujii

    IPC分类号： G11C1124

    CPC分类号： G11C11/412 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

    摘要： A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically connected to the capacitor; a latch circuit located above a silicon substrate, and storing the potential of a storage node of the capacitor; and a bit line connected to the other of the impurity regions of the access transistor T6. At least a portion of the latch circuit is formed above the bit line.

    摘要翻译： 半导体器件包括：电容器：具有杂质区域的存取晶体管，控制存储在电容器中的电荷的输入/输出，其中一个杂质区域电连接到电容器; 位于硅衬底上方的锁存电路，并存储电容器的存储节点的电位; 以及连接到存取晶体管T6的另一个杂质区的位线。 锁存电路的至少一部分形成在位线上方。

    Semiconductor device having impurity regions with varying impurity concentrations
    4.
    发明授权
    Semiconductor device having impurity regions with varying impurity concentrations 失效
    具有杂质浓度不同的杂质区域的半导体装置

    公开(公告)号：US06268627B1

    公开(公告)日：2001-07-31

    申请号：US09198611

    申请日：1998-11-24

    申请人： Yoshiyuki Ishigaki ,  Yasuhiro Fujii

    发明人： Yoshiyuki Ishigaki ,  Yasuhiro Fujii

    IPC分类号： H01L2976

    CPC分类号： H01L27/1108

    摘要： In an access transistor formed on a silicon substrate, its drain region is formed of n− type and n+ type drain regions and its source region is formed of n− type and n+ type source regions. In a driver transistor, its source region is formed of n− type and n++ type source regions and its drain regions is formed of n− type and n+ type drain regions. The n+ +type source region is formed deeper than the n+ type drain region. Accordingly, a semiconductor device ensuring improvement in a static noise margin while suppressing increase in manufacturing cost is provided.

    摘要翻译： 在形成在硅衬底上的存取晶体管中，其漏极区由n型和n +型漏极区形成，其源区由n型和n +型源极区形成。 在驱动晶体管中，其源区由n型和n ++型源极区形成，其漏极区由n型和n +型漏极区形成。 n +型源极区域形成得比n +型漏极区域更深。 因此，提供了一种在抑制制造成本增加的同时确保静态噪声容限的改善的半导体装置。

    Semiconductor device having memory cells and method of manufacturing the same
    7.
    发明授权
    Semiconductor device having memory cells and method of manufacturing the same 失效
    具有存储单元的半导体器件及其制造方法

    公开(公告)号：US06271569B1

    公开(公告)日：2001-08-07

    申请号：US09008594

    申请日：1998-01-16

    申请人： Yoshiyuki Ishigaki ,  Hiroki Honda

    发明人： Yoshiyuki Ishigaki ,  Hiroki Honda

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

    摘要： According to a semiconductor device and a method of manufacturing the same, a storage node has an increased capacity, and a resistance against soft error is improved. A GND interconnection is formed on a first interconnection layer including storage node portions with a dielectric film therebetween. Thereby, the storage node portions, the dielectric film, and the GND interconnection form a capacity element of the storage node portion. The first interconnection layer is arranged symmetrically around the center of the memory cell, and a plurality of memory cells having the same layout and neighboring to each other are arranged along the word lines.

    摘要翻译： 根据半导体器件及其制造方法，存储节点具有增加的容量，并且提高了对软错误的抵抗力。 GND互连形成在包括其间具有介电膜的存储节点部分的第一互连层上。 由此，存储节点部分，电介质膜和GND互连构成存储节点部分的电容元件。 第一互连层围绕存储单元的中心对称布置，并且沿着字线布置具有相同布局并且彼此相邻的多个存储单元。

    SRAM semiconductor device
    8.
    发明授权
    SRAM semiconductor device 失效
    SRAM半导体器件

    公开(公告)号：US5619056A

    公开(公告)日：1997-04-08

    申请号：US693497

    申请日：1996-08-07

    申请人： Hirotada Kuriyama ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

    发明人： Hirotada Kuriyama ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

    IPC分类号： H01L27/11 ,  H01L21/8244 ,  H01L29/76 ,  H01L27/108

    CPC分类号： H01L27/1108 ,  H01L27/11 ,  Y10S257/903

    摘要： The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

    摘要翻译： 本发明提供一种改进的静态随机存取存储器，其可以被制造成通过光刻设计的值。 在第一存储单元和第二存储单元之间的边界处提供用于连接用于第一和第二存储单元的有源区和接地线的第二直接合同。 第二直接接触被分成多个部分。

    Semiconductor device and method of manufacturing thereof
    9.
    发明授权
    Semiconductor device and method of manufacturing thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US5350939A

    公开(公告)日：1994-09-27

    申请号：US37141

    申请日：1993-03-25

    申请人： Hiroki Honda ,  Kimiharu Uga ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

    发明人： Hiroki Honda ,  Kimiharu Uga ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

    IPC分类号： H01L21/74 ,  H01L21/76 ,  H01L27/06 ,  H01L27/08 ,  H01L27/02

    CPC分类号： H01L27/0623

    摘要： An n.sup.- epitaxial layer 4 is formed on the top face of a p type semiconductor substrate 1. A p.sup.+ buried layer 20 is formed by implanting ions in the region extending over the p type semiconductor substrate 1 and the n.sup.- epitaxial layer 4. A p.sup.+ channel stop is formed in the upper layer of the p.sup.+ buried layer 20 by ion implantation. A p well is formed extending from the upper layer of the p.sup.+ channel stop to the top face of the n.sup.- epitaxial layer. An n channel MOS type field effect transistor 200 is formed in the p well 22. It is possible to reliably isolate an element from an adjacent element thereto because of the structure.

    摘要翻译： n型外延层4形成在p型半导体衬底1的顶面上。通过在p型半导体衬底1和n外延层4上延伸的区域中注入离子形成p +埋层20。 通过离子注入在p +掩埋层20的上层形成沟道阻挡层。 形成从p +沟道阻挡层的上层延伸到n外延层的顶面的p阱。 在p阱22中形成n沟道MOS型场效应晶体管200.由于结构，可以将元件与相邻元件可靠地隔离。

    Semiconductor device including complementary insulating gate field effect transistors and bipolar transistors in semiconductor substrate
    10.
    发明授权
    Semiconductor device including complementary insulating gate field effect transistors and bipolar transistors in semiconductor substrate 失效
    半导体器件包括补充绝缘栅场效应晶体管和双极晶体管在半导体衬底

    公开(公告)号：US5245209A

    公开(公告)日：1993-09-14

    申请号：US798096

    申请日：1991-11-27

    申请人： Yoshiyuki Ishigaki

    发明人： Yoshiyuki Ishigaki

    IPC分类号： H01L21/8249 ,  H01L21/74 ,  H01L27/06 ,  H01L27/092

    CPC分类号： H01L21/74 ,  H01L27/0623 ,  H01L27/0921

    摘要： The impurity concentration of an n.sup.+ buried layer 51a in the region for forming a p channel MOS transistor 23 is higher than the impurity concentration of an n.sup.+ buried layer 3a in the region for forming an npn bipolar transistor 21. N.sup.+ buried layers 3a and 51a are formed on a p type silicon substrate 1. An n.sup.- well region 10 is formed as a region for forming npn bipolar transistor 21 on n.sup.+ buried layer 3a. An n well region 12 is formed as a region for forming p channel MOS transistor 23 on n.sup.+ buried layer 51a. While the performance of npn bipolar transistor 21 is maintained, the performance of a CMOS transistor formed of an n channel MOS transistor 22 and p channel MOS transistor 23 is improved. In a Bi-CMOS semiconductor device, the performance of a bipolar transistor portion is maintained, while preventing the formation of a punch through and improving the latch up tolerance of a CMOS transistor portion.

    摘要翻译： 用于形成p沟道MOS晶体管23的区域中的n +掩埋层51a的杂质浓度高于用于形成npn双极晶体管21的区域中的n +掩埋层3a的杂质浓度。形成N +掩埋层3a和51a 在p型硅衬底1上形成n阱区10作为在n +掩埋层3a上形成npn双极晶体管21的区域。 n阱区12形成为在n +掩埋层51a上形成p沟道MOS晶体管23的区域。 在保持npn双极晶体管21的性能的同时，提高了由n沟道MOS晶体管22和p沟道MOS晶体管23构成的​​CMOS晶体管的性能。 在Bi-CMOS半导体器件中，保持双极性晶体管部分的性能，同时防止形成穿孔并提高CMOS晶体管部分的锁存容差。