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80 条记录 (耗时 0.021 秒)

    Phase-locked loop and bias generator
    1.
    发明授权
    Phase-locked loop and bias generator 有权
    锁相环和偏置发生器

    公开(公告)号：US08159275B2

    公开(公告)日：2012-04-17

    申请号：US12627730

    申请日：2009-11-30

    申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08

    摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

    摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

    Semiconductor memory device comprising variable delay unit
    2.
    发明授权
    Semiconductor memory device comprising variable delay unit 有权
    半导体存储器件包括可变延迟单元

    公开(公告)号：US08339877B2

    公开(公告)日：2012-12-25

    申请号：US12764460

    申请日：2010-04-21

    申请人： Sang-Hyup Kwak ,  Seung-Jun Bae ,  Young-Sik Kim

    发明人： Sang-Hyup Kwak ,  Seung-Jun Bae ,  Young-Sik Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/4401 ,  G11C29/50012 ,  G11C2207/2254

    摘要： A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern.

    摘要翻译： 半导体存储器件包括可变延迟单元和数据训练器。 可变延迟单元被配置为根据半导体存储器件是处于数据训练模式还是正常操作模式，通过将写入数据驱动信号延迟不同的时间量来产生写入数据信号，并且还被配置为产生读取 数据驱动信号，通过在数据训练模式和正常操作模式下延迟读取数据信号不同的时间量。 数据训练器被配置为在数据训练模式下被激活，并且被激活时，接收写入数据信号，将写入数据信号与预定的写入模式进行比较，执行数据训练模式操作，并将读出的数据信号输出 预定的读取模式。

    Phase-Locked Loop and Bias Generator
    3.
    发明申请
    Phase-Locked Loop and Bias Generator 有权
    锁相环和偏置发生器

    公开(公告)号：US20100141311A1

    公开(公告)日：2010-06-10

    申请号：US12627730

    申请日：2009-11-30

    申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： H03L7/06 ,  H03K3/01

    CPC分类号： H03L7/08

    摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

    摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

    Voltage-controlled oscillator and phase-locked loop circuit
    6.
    发明授权
    Voltage-controlled oscillator and phase-locked loop circuit 有权
    压控振荡器和锁相环电路

    公开(公告)号：US08400818B2

    公开(公告)日：2013-03-19

    申请号：US13109157

    申请日：2011-05-17

    申请人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： G11C7/00

    CPC分类号： H03B5/1228 ,  G11C7/222 ,  H03B5/1215 ,  H03B5/124

    摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.

    摘要翻译： 压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。 连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。 在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。 连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

    VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT
    7.
    发明申请
    VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT 有权
    电压控制振荡器和相位锁定环路

    公开(公告)号：US20110310659A1

    公开(公告)日：2011-12-22

    申请号：US13109157

    申请日：2011-05-17

    申请人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： G11C11/24 ,  H03B5/12 ,  H03B7/06

    CPC分类号： H03B5/1228 ,  G11C7/222 ,  H03B5/1215 ,  H03B5/124

    摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.

    摘要翻译： 压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。 连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。 在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。 连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

    MEMORY SYSTEM AND METHOD
    9.
    发明申请
    MEMORY SYSTEM AND METHOD 审中-公开
    记忆系统和方法

    公开(公告)号：US20140019833A1

    公开(公告)日：2014-01-16

    申请号：US14031620

    申请日：2013-09-19

    申请人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

    发明人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1004 ,  H03M13/09

    摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

    摘要翻译： 存储器系统包括存储器控制器和存储器件。 存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组 具有来自存储器控制器的命令/地址通过第三通道。

    Data receiver having an integration unit and a sense amplification unit, and semiconductor memory device including the same
    10.
    发明授权
    Data receiver having an integration unit and a sense amplification unit, and semiconductor memory device including the same 有权
    具有集成单元和感测放大单元的数据接收器以及包括该单元的半导体存储器件

    公开(公告)号：US08467255B2

    公开(公告)日：2013-06-18

    申请号：US13162948

    申请日：2011-06-17

    申请人： Dae-Hyun Kim ,  Seung-Jun Bae

    发明人： Dae-Hyun Kim ,  Seung-Jun Bae

    IPC分类号： G11C7/22

    CPC分类号： G11C7/1012 ,  G11C7/1048 ,  G11C7/1084 ,  G11C7/1087

    摘要： A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal

    摘要翻译： 存储器件中的数据接收器包括积分单元，感测放大单元和锁存单元。 积分单元积分数据信号，以响应于采样反馈信号产生第一均衡信号。 数据信号包括顺序接收的多个数据。 感测放大单元响应于感测反馈信号感测第一均衡信号以产生第二均衡信号。 锁存单元锁存第二均衡信号以产生采样数据信号